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? L64780 dvb-t cofdm demodulator order no. i14027 technical manual february 2000
ii this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?cer of lsi logic corporation. document db14-000113-00, first edition (february 2000) this document describes lsi logic corporations L64780 dvb-t cofdm demodulator and will remain the of?cial reference source for all revisions/releases of this product until rescinded by an update. to receive product literature, visit us at http://www.lsilogic.com. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. trademark acknowledgment the lsi logic logo design and g10 are registered trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies. copyright ? 1999, 2000 by lsi logic corporation. all rights reserved.
preface iii preface this book is the primary reference and technical manual for the L64780 dvb-t cofdm demodulator. it contains a complete functional description as well as complete physical and electrical speci?cations for the lsi logic L64780. audience this document assumes you are familiar with digital video broadcasting, terrestrial television transmission and reception, modulation/demodulation, error control coding, digital signal processing, microprocessors, and related support devices. the people who bene?t from this book are: engineers and managers evaluating the L64780 for use in a receiver for digital tv or cable data transmissions. engineers designing the L64780 into a system. organization this document has the following chapters and appendixes: chapter 1, introduction , provides a brief overview of the L64780 and lists its features and bene?ts . chapter 2, architectural overview , describes the architecture of the L64780 and gives a functional description of its main components. chapter 3, interfaces , describes the interfaces of the L64780 and gives a functional description of each. chapter 4, register descriptions , provides a description of the registers that determine the functionality of the L64780.
iv preface chapter 5, signal descriptions , provides a description of the signals used and generated by the L64780. chapter 6, speci?cations , describes the speci?cations for the L64780 electrical and mechanical characteristics. appendix a, programming the L64780 using the serial bus interface , describes how to program the L64780 using the serial bus. related publications etsi speci?cation ets 300 744. 1997. digital broadcasting systems for television, sound and data services; framing structure, channel coding and modulation for digital terrestrial television. stott, j.h., 1996. the dvb terrestrial (dvb-t) speci?cation and its implementation in a practical modem . international broadcasting convention 1996. conventions used in this manual the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. hexadecimal numbers are indicated by the pre?x 0x (for example, 0x32cf). binary numbers are indicated by the pre?x 0b (for example, 0b0011.0010.1100.1111).
contents v contents chapter 1 introduction 1.1 overview 1-1 1.2 using the L64780 in a receiver 1-3 1.3 rf tuner block functions 1-4 1.4 modes of operation 1-6 1.5 features 1-6 1.6 typical performance 1-7 chapter 2 architectural overview 2.1 demodulator module functional description 2-2 2.2 analog-to-digital converter (adc) 2-4 2.3 automatic gain control (agc) 2-4 2.3.1 agc target rms value 2-4 2.3.2 agc external loop filter 2-5 2.3.3 agc loop gain ks 2-6 2.4 real-to-complex conversion 2-7 2.5 fast fourier transform (fft) block 2-8 2.6 time synchronization 2-8 2.6.1 timing loop gain 2-8 2.6.2 tim_clk_init register de?nition 2-9 2.6.3 tim external loop filter 2-9 2.7 automatic frequency control (afc) 2-10 2.7.1 analog frequency synchronization 2-10 2.7.2 digital frequency synchronization 2-10 2.7.3 afc loop gain 2-11 2.7.4 afc_init_freq register de?nition 2-12 2.7.5 afc external loop filter 2-12 2.8 tps decoding and frame synchronization 2-13 2.9 mode control logic 2-14
vi contents 2.10 channel estimation and equalization 2-15 2.11 viterbi metric assignment and quantization 2-16 2.12 symbol deinterleaver 2-17 2.13 bit deinterleaver 2-17 chapter 3 interfaces 3.1 output interface 3-1 3.1.1 output format in nonhierarchical mode 3-1 3.1.2 output format in hierarchical mode 3-5 3.2 muxin interface 3-8 3.2.1 access to timing and ddfs blocks 3-10 3.2.2 access to the afc block 3-10 3.2.3 access to the fft block 3-11 3.2.4 access to the csi block 3-11 3.2.5 access to the sdi block 3-12 3.3 muxout interface 3-13 3.3.1 ddfs output 3-14 3.3.2 fft output 3-14 3.3.3 afc output 3-14 3.3.4 channel equalizer (ce) output 3-15 3.3.5 csi output 3-15 3.3.6 adc output 3-16 3.4 microprocessor interface 3-16 chapter 4 register descriptions 4.1 memory map 4-2 4.2 interrupt registers 4-7 4.2.1 address line 0x00 4-7 4.2.2 interrupt mask register, address line 0x01 4-9 4.3 tps registers 4-11 4.3.1 address line 0x02 4-11 4.3.2 address line 0x03 4-12 4.3.3 address line 0x04 4-14 4.4 parameter registers 4-16 4.4.1 address line 0x05 4-16 4.4.2 address lines 0x06, 0x07, 0x08 4-19 4.4.3 address line 0x09 4-20
contents vii 4.4.4 address line 0x0a 4-23 4.4.5 address line 0x0b 4-24 4.4.6 address line 0x0c 4-25 4.4.7 address line 0x0d 4-27 4.4.8 address line 0x0e 4-27 4.4.9 address lines 0x0f, 0x10 4-28 4.4.10 address line 0x11 4-29 4.4.11 address line 0x12 4-30 4.4.12 address line 0x13 4-31 4.4.13 address line 0x14 4-31 4.5 mux register address line 0x15 4-32 4.6 performance monitoring registers address line 0x16 4-34 4.6.1 address line 0x17 4-35 4.6.2 address line 0x18 4-35 4.7 mode register address line 0x19 4-36 4.8 3-wires register address line 0x1a 4-38 chapter 5 signal descriptions 5.1 overview 5-1 5.2 microprocessor interface 5-3 5.3 main signals 5-4 5.4 sigma-delta outputs 5-6 5.5 mux signals 5-6 5.6 3-wires signals 5-7 5.7 jtag signals 5-7 5.8 test pins 5-8 5.9 asic pins 5-8 5.10 pll pins 5-8 5.11 tester pins 5-9 chapter 6 speci?cations 6.1 electrical speci?cations 6-1 6.2 ac timing 6-4 6.2.1 input data interface 6-4 6.2.2 output data interface 6-5 6.2.3 reset timing 6-5 6.3 signal speci?cations 6-6
viii contents 6.4 pinouts 6-11 6.4.1 pin list 6-11 6.4.2 pin layout 6-14 6.5 mechanical drawing 6-15 appendix a programming the L64780 using the serial bus interface a.1 serial bus protocol overview a-2 a.2 programming the slave address using the serial bus a-3 a.2.1 write cycle using the serial bus a-3 a.2.2 read cycle using the serial bus a-4 customer feedback figures 1.1 typical terrestrial-only receiver 1-3 1.2 uhf tuner example 1-4 1.3 receiver architecture for satellite and terrestrial reception 1-5 1.4 performance with additive write gaussian noise (awgn) 1-7 1.5 dvb-t carrier to co-channel pal-i interference ratio for failure 1-8 1.6 maximum level of a single echo for failure of qpsk, rate 1/2, guard interval 7 1-8 2.1 dttv demodulator architecture 2-3 2.2 structure of 9-bit agc_target register 2-4 2.3 agc loop pass filter 2-5 2.4 external low-pass loop filter 2-9 2.5 afc loop pass filter 2-12 2.6 scattered pilot structure 2-15 3.1 output interface in nonhierarchical and serial modes 3-2 3.2 nonhierarchical, serial mode, 64 qam constellation 3-2 3.3 nonhierarchical, serial mode, 16 qam constellation 3-3 3.4 nonhierarchical, serial mode, qpsk constellation 3-3 3.5 output interface in nonhierarchical and parallel modes 3-3 3.6 nonhierarchical, parallel mode, 64 qam constellation 3-4 3.7 nonhierarchical, parallel mode, 16 qam constellation 3-4
contents ix 3.8 nonhierarchical, parallel mode, qpsk constellation 3-4 3.9 output interface in hierarchical and two fecs modes 3-5 3.10 hierarchical, two fec decoders, 16 qam constellation 3-5 3.11 hierarchical, two fec decoders, 64 qam constellation 3-6 3.12 output interface in hierarchical and one fec mode 3-6 3.13 hierarchical, one fec decoder mode with 16 qam (hp or lp selected) or 64 qam (lp selected only) 3-7 3.14 hierarchical, one fec decoder mode with 64 qam (hp selected only) 3-7 3.15 muxin signals interface 3-8 3.16 timing and ddfs input mapping 3-10 3.17 afc input mapping 3-10 3.18 fft input mapping 3-11 3.19 csi input mapping 3-11 3.20 sdi input mappings 3-12 3.21 d[23:0] bus mapping in three-bit soft decision 3-12 3.22 d[23:0] bus mapping in four-bit soft decision 3-12 3.23 ddfs output mapping 3-14 3.24 fft output mapping 3-14 3.25 afc output mappings 3-14 3.26 ce output mappings 3-15 3.27 csi output mappings 3-15 3.28 adc output mapping 3-16 4.1 graphical view of the L64780 register address space 1 4-4 4.2 graphical view of the L64780 register address space 2 4-5 4.3 graphical view of the L64780 register address space 3 4-6 4.4 interrupt generation 4-9 5.1 L64780 logic symbol 5-2 6.1 input data ac timing 6-4 6.2 output data ac timing 6-5 6.3 reset timing 6-5 6.4 package pin layout 6-14 6.5 160 pqfp mechanical drawing: top and side views 6-15 6.6 160 pqfp mechanical drawing: detail 6-16 a.1 serial bus overview a-2 a.2 general call address a-3
x contents tables 2.1 approximate and exact frequencies for real to complex conversion 2-7 3.1 muxinbus mapping 3-8 3.2 muxin conifguration 3-9 3.3 muxout_select word de?nition 3-13 3.4 mode selection using the p_s input signal 3-16 4.1 L64780 registers and internal memory map 4-2 4.2 ddfs block modes 4-21 4.3 muxin signal settings and muxin clock 4-33 6.1 absolute maximum ratings 6-1 6.2 recommended operating conditions 6-2 6.3 dc characteristics 6-2 6.4 input data ac timing parameters 6-4 6.5 output data ac timing parameters 6-5 6.6 reset ac timing parameters 6-5 6.7 signal summary list 6-6
L64780 dvb-t ofdm demodulator 1-1 chapter 1 introduction this chapter provides an overview of the lsi logic L64780 dvb-t cofdm demodulator. it also lists this chips features and bene?ts, and provides an illustrated description of its typical performance. this chapter contains the following sections: section 1.1, overview, page 1-1 section 1.2, using the L64780 in a receiver, page 1-3 section 1.3, rf tuner block functions, page 1-4 section 1.4, modes of operation, page 1-6 section 1.5, features, page 1-6 section 1.6, typical performance, page 1-7 1.1 overview the L64780 is part of a digital terrestrial television receiver for signals transmitted in accordance with the digital video broadcasting- terrestrial/european telecommunications standards institute (dvb-t/etsi) speci?cation. these signals convey digital information using coded orthogonal frequency division multiplexing (cofdm), as well as concatenated reed-solomon and convolutional forward error correction (fec) techniques. this information payload takes the form of an mpeg-2 transport stream that conveys picture, sound, and data information. this mpeg-2 transport stream format is used also in related speci?cations for the transmission of digital television signals by satellite or cable.
1-2 introduction the concatenated coding used in the dvb-t/etsi speci?cation is identical to that in the dvb-s speci?cation for satellite transmissions. the fec decoder can take the same form in receivers for satellite as well as terrestrial transmissions. thus, the L64780 chip provides all the necessary demodulation functions except for fec decoding, which is done by a separate chip, such as the l64724 or the l64705. the L64780 i/o format and pinouts simplify its connection to the l64724/l64705. the dvb-t/etsi speci?cation incorporates many modes, providing a wide range of capacity/performance trade-off options. the L64780 demodulates all these modes. terrestrial transmission paths are prone to multipath, which can result in ghosting on analog television pictures. with conventional methods of digital transmission, multipath causes inter-symbol interference. this becomes increasingly problematic as the bit rate increases. the dvb-t/etsi speci?cation uses a special form of modulation that uses coded orthogonal frequency division multiplexing, which is well-suited to channels with signi?cant multipath. it can tolerate signals with long delay and high relative amplitude. consequently, the L64780 can accommodate natural multipath (from terrain, buildings, etc.) and it can be used in a single frequency network (sfn). in an sfn, many transmitters operate on the same frequency with the same modulation (used in digital audio broadcasting, which also uses cofdm). in the frequency domain, multipath can be seen as channel frequency selectivity. cofdm applies concatenated fec coding, then distributes the coded data over many carriers (1705 or 6817 in this case, depending on the mode). at the receiver, the frequency selectivity of the channel causes some carriers to be degraded or suppressed. however, the receiver can determine how much each carrier is affected by noise, then pass this information to the inner-code viterbi decoder by means of soft-decision bits. this allows the viterbi decoder to decode the data more ef?ciently. a second decoder, for the reed-solomon fec, completes the process.
using the L64780 in a receiver 1-3 1.2 using the L64780 in a receiver the L64780 provides those parts of a receiver for dvb-t signals that are exclusive to the terrestrial speci?cation for cofdm demodulation and inner interleaving. this includes synchronization, channel-equalization, and derivation of channel-state information. the combination of the lsi logic L64780 and l64724 (or l64705) chips forms the core of a receiver design for dvb-t, supporting two possible approaches: exclusively dvb-t reception, and dual dvb-t/dvb-s reception (see figure 1.1 ). figure 1.1 typical terrestrial-only receiver figure 1.1 shows the basic structure for a terrestrial-only receiver. the uhf (or, possibly, vhf) signal from the antenna passes through a tuner module that delivers a low intermediate frequency (if) signal to the L64780 chip by means of an analog-to-digital converter (adc). the L64780 chip performs all the essential functions for cofdm demodulation, excluding the ?nal steps of error correction. it requires a sampling-frequency clock oscillator (at f clk18 mhz), for which it provides the control voltage to lock its frequency to the desired value. the L64780 chip delivers soft-decision information to the l64705 or l64724 chip, vcxo tuner L64780 afc agc ts mpeg a/v decoder l64005 mpeg ts demux system cpu l64118 l64724 f clk18 agc (automatic gain control) afc (automatic frequency control)
1-4 introduction which then completes the error correction, delivering an mpeg-2 transport stream. other mpeg-standard lsi logic chips (for example, l64118 and l64005) can then be used to demultiplex the mpeg-2 transport stream into its coded audio, coded video, and data components, handle conditional access, and decode the audio and video signals for presentation to the display and loudspeakers. in figure 1.1 , the microprocessor is embedded in the l64118. it controls rf-channel selection, mode selection for the L64780 chip, and program selection for the mpeg demultiplexer. 1.3 rf tuner block functions figure 1.2 indicates the functions performed within the rf tuner block. the example uses a double-conversion approach, in which the rf tuner converts the uhf signal to a ?rst if (if1, where ?ltering, ampli?cation, and gain control are done) followed by another conversion to the second low if, (if2), required at the input of the L64780. figure 1.2 uhf tuner example tracking rf filter if 1 filter if 2 filter lo 1 lo 2 L64780
rf tuner block functions 1-5 figure 1.3 illustrates how terrestrial and satellite reception can be combined in one unit. for satellite reception, the if signal (for example, from 1 to 2 ghz) from the dish unit is fed into a satellite tuner. this tuner: 1. selects one rf signal from the 1 to 2 ghz range 2. converts the signal to one or more intermediate frequencies 3. down-converts the signal to base band 4. feeds its i and q components into the l64724 single-chip dvb-s satellite receiver the l64724: 1. samples the i and q baseband signals 2. demodulates the qpsk 3. processes the error correction functions the l64724 also implements a bypass of the adc and demodulation functions. thus, it can accept the soft decisions delivered by L64780 and feed them directly to the viterbi decoder. this architecture implements a cost-effective solution for mixed satellite and terrestrial front-ends. figure 1.3 receiver architecture for satellite and terrestrial reception satellite tuner mpeg transport stream l64724 terrestrial tuner L64780 uhf/vhf l-band
1-6 introduction 1.4 modes of operation the L64780 supports all the modes of the dvb-t speci?cation, including: 2 k and 8 k fft sizes nonhierarchical qpsk, 16 qam, and 64 qam constellations hierarchical 16 qam and 64 qam constellations constellation scale factors a =1,2,and4 code rates of 1/2, 2/3, 3/4, 5/6, and 7/8 guard intervals of 1/4, 1/8, 1/16, and 1/32 1.5 features the L64780 features include: dvb-t compliance internal or external dac digital real-to-complex conversion spectrum inversion 2 k or 8 k fft size rapid time synchronization rapid frequency synchronization common phase error correction high-order ?lter for frequency interpolation automatic mode switching automatic frame detection use of channel state information for protection against multipath and interference 3- or 4-bit soft decision outputs analog or digital afc agc
typical performance 1-7 stand-alone fft mode (forward or inverse) easy connection to the l64705 or l64724 for fec 160-pin pqfp package 1.6 typical performance figure 1.4 illustrates the target performance of the L64780 compared to the simulation results in the etsi speci?cation for all the nonhierarchical modes in a gaussian channel. differences between the target performance and the simulations are accounted for as follows: about 1.5 db for the noisy reference effect in the channel equalizer 0.1C0.3 db for noise on the channel state measurement it is not possible to be speci?c about the source of the remaining small difference (about 0.4 db) because we do not have enough information about the conditions under which the simulations were performed. the two losses (in the channel equalizer and channel state information) are compromises made in the interests of the speed of tracking of a time-varying channel. sacri?cing the tracking ability reduces the losses. figure 1.4 performance with additive write gaussian noise (awgn) 25 20 15 10 5 0 1/2 2/3 3/4 5/6 7/8 1/2 2/3 3/4 5/6 7/8 1/2 2/3 3/4 5/6 7/8 qpsk 16 qam 64 qam cin (db) measured qef simulated qef from speci?cation
1-8 introduction figure 1.5 illustrates the target protection ratio of pal-i into dvb-t. the point indicated by carriers coincident about here shows the point where the vision carrier of the pal-i signal lines up directly with one of the carriers on the odfm frequency raster. figure 1.5 dvb-t carrier to co-channel pal-i interference ratio for failure figure 1.6 illustrates the maximum level of echo acceptable to the demodulator. the graph shows that in the selected mode, the demodulator works without failure inside the guard interval and without failure signi?cantly outside it. figure 1.6 maximum level of a single echo for failure of qpsk, rate 1/2, guard interval 7 2 0 - 2 - 4 - 6 - 8 - 10 - 12 - 2500 - 1500 - 500 500 1500 2500 less robust more robust normal frequency offset (hz) 64 qam rate 2/3 16 qam rate 3/4 qpsk rate 1/2 cin (db) carriers coincident about here 0 - 2 - 4 - 6 - 8 - 10 0102030405060708090100 delay ( m s) relative level no failure for echo here.
L64780 dvb-t ofdm demodulator 2-1 chapter 2 architectural overview this chapter describes the L64780 architecture and provides a functional description of each of its components. it contains the following sections: section 2.1, demodulator module functional description, page 2-2 section 2.2, analog-to-digital converter (adc), page 2-4 section 2.3, automatic gain control (agc), page 2-4 section 2.4, real-to-complex conversion, page 2-7 section 2.5, fast fourier transform (fft) block, page 2-8 section 2.6, time synchronization, page 2-8 section 2.7, automatic frequency control (afc), page 2-10 section 2.8, tps decoding and frame synchronization, page 2-13 section 2.9, mode control logic, page 2-14 section 2.10, channel estimation and equalization, page 2-15 section 2.11, viterbi metric assignment and quantization, page 2-16 section 2.12, symbol deinterleaver, page 2-17 section 2.13, bit deinterleaver, page 2-17
2-2 architectural overview 2.1 demodulator module functional description the components of the L64780 are integrated to provide a complete system solution for demodulation of terrestrial and satellite originated signals. figure 2.1 shows the components of the L64780 and indicates their interaction. these components are described in the following sections.
demodulator module functional description 2-3 figure 2.1 dttv demodulator architecture low if input agc detect real to complex adc frequency shift fft frequency sync time sync sd cpe correction channel estimation viterbi metrics quantize symbol deintlv. bit deintlv. microprocessor interface tps decoder vcxo csi frame pulse con?guration information analog afc control agc control digital guard interval con?guration and fft size afc control sd to fec output interface. & equalization fft = fast fourier transform adc = analog-to-digital converter vcxo = voltage-controlled crystal oscillator sd = sigma-delta csi = channel state information
2-4 architectural overview 2.2 analog-to-digital converter (adc) features of the L64780 analog-to-digital converter include: low-if center frequency input: 4.57 mhz input bandwidth: 8 mhz sampling clock: 18.29 mhz resolution: 8-bit the L64780 also offers a 10-bit parallel port for connection to an external, 10-bit adc. 2.3 automatic gain control (agc) the tuner agc ampli?er ampli?es the signal. the resulting signal has an rms value of . the agc ampli?es this signal so that its variance allows the fft to work properly. to do this, the input signal power must be 10.95 db down on the maximum adc input range, normalized to 1.0. this means the rms value of the input to the L64780 is: . 2.3.1 agc target rms value figure 2.2 de?nes the nine-bit agc_target register. figure 2.2 structure of 9-bit agc_target register for the fft to perform correctly, the input level of the cofdm signal must be 10.95 db down on the normalized 1.0 input range. thus, the target rms value, s , of the input signal must be 0.283, as shown in equation 2.1. equation 2.1 s 0 s 0 0.283 = s t b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 agc_target_msb[5:0] agc_target_lsb[5:0] s t 512 2 p -- - s =
automatic gain control (agc) 2-5 since the recommended rms value is , the recommended value is , resulting in an agc_target initial value of 0x74 (0b0111.0100). thus: agc_target_lsb = 0x4 (0b100) agc_target_msb = 0x0e (0b01110) also see the description in section 4.4.4, address line 0x0a, page 4-23 . 2.3.2 agc external loop filter the input power control signal drives the sigma delta modulated output, agcout. use the agcout signal to drive an external passive rc ?lter that feeds the gain control stage, as shown in figure 2.3 . figure 2.3 agc loop pass filter the r and c values for the low-pass ?lter must meet the following requirement: equation 2.2 r agc c agc = 560 m s see figure 2.3 for the recommended values. s 0 . 283 = s t s 0.226 = r agc = 56 k w c agc = 10 nf r= 5.6 k w agcout 5v
2-6 architectural overview 2.3.3 agc loop gain k s the gain of the loop, k s , must obey the following rule: equation 2.3 where: f is the slope of the tuner agc characteristics in db/v. is the target value for the input signal. with an rms value of , and a tuner characteristic of 50 db/v, the loop gain is: equation 2.4 to code k s , lsi logic uses an approximation to the nearest power of 2. lsi logic uses the agc_gain[2:0] register, with the following correspondence: equation 2.5 because the number of values agc_gain can have is limited, so are those of k s . thus, equation 2.6 in our example, agc_gai n=4isthe most appropriate value, giving a value of: equation 2.7 the real-to-complex block takes the input samples from the adc output and converts them into a complex baseband representation for input to the fft block. k s 8.5 10 5 C f s t -------------------------- = s t s 0.283 = k s 7.5 10 6 C = k s 2 8 C 2 agc_gain C ? agc_gain k s log 22 log --------------- 4 C ? k s 1.52 10 5 C ?
real-to-complex conversion 2-7 2.4 real-to-complex conversion the dvb-t signal occupies a bandwidth of approximately 7.61 mhz; the signal is symmetrically disposed in extent about a notional center carrier. as radiated, this normally lies in the uhf range; however, its spectrum is not symmetrical, because its upper and lower sidebands are different (a double-sideband modulated signal does have a symmetrical spectrum). thus, a complex representation is needed to describe it at baseband. this spectrum can be derived using the in-phase i and quadrature-phase q demodulators, but each would have to be sampled separately, using two adcs and many well-matched components. the L64780 chip avoids the complexity and expensive matching of analog components. it uses a single adc, and derives the complex- baseband representation by internal digital processing. the adc samples the dvb-t signal at a low if, then the real-to-complex block digitally shifts the samples to complex baseband form, centered on zero frequency. it is fundamental to the operation of this conversion processing that the nominal center frequency (f lif ) of the low if is related to the sampling frequency, f clk18 , used by the adc (see table 2.1 , which shows that f clk18 =4f lif almost exactly). the afc circuitry of the L64780 ensures that this is the case. the output of the block is complex numbers at the rate of f clk18 /2. the frequencies in table 2.1 apply for the normal version of the dvb-t speci?cation for use with uhf channels spaced by 8 mhz. to adopt the dvb-t speci?cation for use with 7 mhz or 6 mhz channel spacing, scale the clock frequency and all other frequencies within the system (including the bit-rate capacity and low if) by factors of 7/8 and 6/8, respectively. table 2.1 approximate and exact frequencies for real to complex conversion symbol approx. frequency, mhz exact frequency, mhz adc sampling frequency f clk18 18.28 128/7 low-if center frequency f lif 4.57 32/7
2-8 architectural overview 2.5 fast fourier transform (fft) block the fft block converts from the temporal to the frequency domain representation. it has the following modes of operation: fft and inverse fft 2 k (2048 points) and 8 k (8192 points) mode 2.6 time synchronization this block ?nds the optimum timing for the start of the fft window, and synchronizes the frequency of the clock, f clk18 , to the received signal the options for the duration of the symbol and the duration of the guard interval are given in paragraph 4.4 of the dvb-t/etsi speci?cation. the block takes the sequence of complex numbers from the real-to- complex conversion block and, to synchronize the clock, produces a control signal for the voltage-controlled oscillator. the control voltage of the vcxo is converted into a sigma-delta ( s/d ) modulated signal and output as a single wire signal. this signal requires external low-pass ?ltering to extract its mean value, which represents the control voltage of the oscillator. the transmitter repeats a segment of the signal during the guard interval. this block detects the repeated portion of the signal. the signal processing resists impairment from high levels of echoes or interference. 2.6.1 timing loop gain in 2 k mode, the optimal iirgain is 0b01, or . this leads to k i and k p values of: equation 2.8 in 8 k mode, the optimal iirgain is 0b11, or . a 3.125 10 2 C ? k i 1.69 k vcxo ------------------ = k p 512 k i = a 7.8 10 3 C ?
time synchronization 2-9 this leads to k i and k p values equal to: equation 2.9 2.6.2 tim_clk_init register de?nition the tim_clk_init register is de?ned as a twos complement 15-bit register that has the following meaning: equation 2.10 where w 0 is the central frequency of the vcxo. 2.6.3 tim external loop filter the control voltage signal of the vcxo drives the sigma delta modulated output, vcxout. use the vcxout to drive an external passive rc ?lter that feeds the timing clock control stage. see figure 2.4 . figure 2.4 external low-pass loop filter the - 3 db cutoff frequency of this system is f 0 = 212 hz, giving an estimate of the tim loop bandwidth and resulting in a low-pass ?lter time constant t1 = rc = 750 m s. the r and c values for the low-pass ?lter must meet the following requirement: r tim c tim = 750 m s. k i 0.1 k vcxo ------------------ = k p 512 k i = w i w 0 5k vcxo tim_clk_init 2 15 ------------------------------------------------------------------- + = r tim = 10 k w c tim = 75 nf r= 1 k w vcxout 5v
2-10 architectural overview 2.7 automatic frequency control (afc) the two methods for applying the correction required to achieve frequency synchronization are analog and digital. the method used depends on the design of the analog tuner. the L64780 allows both options, which are described in the following subsections. 2.7.1 analog frequency synchronization this block adjusts the frequency of the local oscillator in the tuner so that the center frequency of the low if is equal to its nominal value of f lif . the adjustment must be accurate to within a small fraction of the carrier spacing, so that intercarrier interference is kept to an acceptably low level and the tracking ability of the channel estimation is not absorbed in correcting for the error in the frequency of the local oscillator. the block takes the sequence of complex numbers from the output of the fft block and produces a control signal for the local oscillator. this control signal is delivered as a single-wire sigma-delta ( s/d ) signal. the initial error in the frequency of the local oscillator can be several times the carrier spacing; the measurement of the frequency error relies on the continual pilot carriers. the measurement range is 51.7 khz in the 8k mode and 143 khz in the 2k mode. the oscillator control signal is derived from the measured frequency error. the value of the control signal can also be read and initialized through the microprocessor interface, which allows a previously stored value to be used when a channel is selected, making acquisition faster. 2.7.2 digital frequency synchronization this block uses digital signal processing (dsp) to correct for the tolerance in the frequency of the local oscillator in the tuner. the dsp shifts the frequency of the complex baseband signal so that its center frequency is zero. the shift needs to be accurate to within a small fraction of the carrier spacing so that intercarrier interference is kept to an acceptably low level and so the tracking ability of the channel estimation is not absorbed in correcting for the error in the frequency of the local oscillator.
automatic frequency control (afc) 2-11 the block takes the sequence of complex numbers from the output of the fft block and produces a numerical control signal. it also takes the sequence of complex numbers from the real-to-complex conversion block and applies the frequency shift to the numbers according to the numerical control signal. then, it passes the data on to the fft block. the digital frequency synchronization block comprises two parts: one to shift the frequency of the complex baseband signal, and one to measure the error in the center frequency of the complex baseband signal as presented to the fft block. multiplying the signal by a rotating vector shifts the frequency of the complex baseband signal. a number-controlled oscillator (nco) with sine and cosine outputs generates the rotating vector. the frequency range of the nco is 143 khz. the error in the frequency of the local oscillator translates directly into an error in the center frequency of the complex baseband signal. the range of measurement is 51.7 khz in the 8 k mode, and 143 khz in the 2 k mode. the numerical control signal is derived from the measured frequency error. use the microprocessor interface to read and initialize the value of the control signal. this allows a previously stored value to be used when a channel is selected, thus making acquisition faster. 2.7.3 afc loop gain in digital afc mode, the optimal sensitivity (ksens) is when the afc_sensitivity ?eld in the parameter registers (see page 4-18 )is set to 0b110: equation 2.11 in analog afc mode, the optimal afc_sensitivity is de?ned as: equation 2.12 k sens 1.56 ? 10 2 C k sens 74.4 k vcxo ----------------- =
2-12 architectural overview 2.7.4 afc_init_freq register de?nition in afc digital loop mode, the afc_init_freq register is de?ned as a twos complement 24-bit register with the following usage: equation 2.13 where w 0 is the central frequency of the vcxo. in afc analog loop mode, the afc_init_freq register is de?ned as a twos complement 24-bit register and in the L64780 has the following usage: equation 2.14 where w 0 is the frequency of the vcxo. 2.7.5 afc external loop filter the control signal of the frequency loop drives the sigma-delta modulated output afcout. use the afcout signal to drive an external passive rc ?lter that feeds the timing clock control stage, as shown in figure 2.5 . figure 2.5 afc loop pass filter the - 3 db cutoff frequency of this circuit is f 0 = 482 hz, giving a rough estimate of the frequency loop bandwidth and resulting in a low-pass ?lter time constant: equation 2.15 w i w 0 143 10 3 2 23 ------------------------- afc_init_freq ? ? ?? + = w i w 0 5k vcxo 2 20 ------------------ afc_init_freq ? ? ?? + = r afc = 100 k w c afc = 3.3 nf r= 10 k w afcout 5v t 1 rc 300 m s ==
tps decoding and frame synchronization 2-13 the r and c values for the low-pass ?lter must meet the requirement shown in equation 2.16 : equation 2.16 2.8 tps decoding and frame synchronization this block takes the sequence of complex numbers from the output of the fft block and recovers the transmission parameter signalling (tps) data de?ned in paragraph 4.6 of the dvb-t/etsi speci?cation. the block passes the resulting data to the control logic of the L64780; it thus con?gures the mode of operation of much of the demodulators circuitry. the tps data contains information on: the modulation system whether the transmission is hierarchical what the value of a is (if the transmission is hierarchical) the inner code rate(s) the guard interval the mode: 2 k or 8 k the guard interval and mode interaction cannot be used for acquisition, but assist the receiver in handling a recon?guration of the transmission. by implication, the tps also indicates the phase of the four-symbol sequence of insertion of scattered pilots. the tps decoder extracts the data bits from the tps carriers and retains the most recent 67 bits. the decoder detects the start of the frame and carries out the bose-chaudhuri-hocque (bch) error check on the block of 67 bits, so that data containing errors can be discarded. all the data in the list above are passed to the control logic along with two ?ags: one indicates the start of a frame; the other indicates whether the error check detects errors. if there were no errors, the control logic uses the data to con?gure the demodulator, discarding any previous settings. the settings can be read and initialized through the microprocessor interface, which allows previously stored settings to be used when a channel is selected, making acquisition faster. r afc c afc 330 m s =
2-14 architectural overview 2.9 mode control logic if previously stored mode data are available, they are used when a channel is selected or when the signal strength rises after a period of signal loss. this is done by the means of an external microprocessor and makes acquisition faster. when the mode control logic becomes an error-free tps block, mode data from that tps block replaces any previously determined mode data. in this context, the mode data consists of: 2 k or 8 k mode length of the guard interval modulation system hierarchy information inner code rate the mode control logic con?gures all the demodulator blocks whose operation is affected by these parameters. acquisition of the demodulator is outlined in the following steps: 1. achieve full synchronization of the fft start and the clock frequency. 2. make coarse and ?ne automatic frequency control (afc) corrections, and achieve frequency synchronization. 3. equalize the channel frequency response, once the symbol number is zero. 4. wait up to one frame for the start of a tps block, and wait another frame for the complete tps block to be received. there is a wait of one or more additional frames, if necessary, until a tps block is received without errors. 5. the modulation system, hierarchy information, and code rate from the tps data are used to con?gure the viterbi metric assignment block, and, by means of the microprocessor interface, the external viterbi decoder(s).
channel estimation and equalization 2-15 2.10 channel estimation and equalization the output from the fft block is a sequence of complex numbers, each describing the signal received on one of the cofdm carriers. the numbers correspond to the values, chosen from the points of the current constellation, which were used to modulate each carrier at the modulator. however, each carrier is received with unknown amplitude and phase due to the combined effects of: the channel through which the rf signal has passed (which, in general, is frequency selective) any minor error in the fft timing window the purpose of the channel estimation and equalization block is to correct these effects so that the complex numbers at its output would, if plotted on an argand diagram, correspond to points of the transmitted constellation (for example, qpsk, 16 qam, or 64 qam) except for any superimposed noise or interference. the transmitted dvb-t signal contains scattered pilots, which are distributed among the data cells in a regular pattern (see figure 2.6 ). these are transmitted with known values: the imaginary part is always zero, while the real part has a ?xed amplitude. the sign of the real part, however, is determined by the carrier number (according to a pseudo- random function that also is used in a similar way to determine the real part of continual pilots). figure 2.6 scattered pilot structure the channel estimation and equalization block compares each received scattered-pilot cell with the known transmitted value (derived from a symbol 67 symbol 0 symbol 1 symbol 2 symbol 3 k min = 0 k max = 1704 if 2k k max = 6816 if 8k
2-16 architectural overview prbs generator) to obtain a snapshot of the response of the channel (including any timing uncertainty) for the corresponding carrier at that time instant. the data cells that must be corrected lie between the scattered pilots, in both frequency and time. this allows for appropriately generated corrections for each data cell by using a suitable form of interpolation applied to the measured values of the scattered pilots. as well as obtaining in-between values of the channel response, the interpolator also slightly reduces the effects of thermal noise on the scattered-pilot measurements. the reduction in noise and the fact that scattered pilots are transmitted with a power approximately 2.5 db greater than data cells, keeps the inevitable loss of performance due to scattered-pilot noise within acceptable bounds. 2.11 viterbi metric assignment and quantization this block takes in the sequence of complex numbers, each describing the signal received on one of the cofdm carriers, after equalization. these are the received versions of the complex numbers chosen at the modulator from the points of the current constellation, according to the coded bits to be sent. this block forms viterbi metrics (soft decisions) for each of the received bits. these metrics are quantized and passed on, after reordering in the deinterleaver stages, to the associated viterbi convolutional decoder. the use of soft rather than hard decisions is vital to obtaining the rugged properties of cofdm. the associated viterbi convolutional decoder, which resides on a separate chip (for example, the lsi logic l64724), is capable of accepting soft decisions that are quantized to either three or four bits. three bits are required for acceptable performance, while four bits improve the performance for higher-order modulation options of the dvb- t speci?cation, especially with non-uniform constellations. decoder chips designed primarily for qpsk or bpsk modulation commonly use three bits because the advantage of using four bits is minimal. the L64780 chip provides 4-bit soft decisions, but it also can be used to drive 3-bit decoders.
symbol deinterleaver 2-17 2.12 symbol deinterleaver from each received constellation point, the viterbi metric assignment block extracts up to six soft decisions. the symbol deinterleaver accepts one cofdm symbol containing soft decisions and reorders them according to an algorithm de?ned in the dvb-t speci?cation. it then passes this reordered data to the bit deinterleaver. echoes cause minima (holes) in the received spectrum, leading to groups of carriers on which the data is unreliable. for optimum operation of the viterbi decoder, these groups of unreliable carriers must be split up. the symbol deinterleaver ful?lls part of this function; the remainder is done by the bit deinterleaver. in 2 k mode, there are 1705 cofdm carriers, of which 1512 in each symbol carry data. each of these carriers yields either 2 (qpsk), 4 (16 qam), or 6 (64 qam) soft decisions. each of these soft decisions consists of four bits of information. the effect of the operation of the symbol deinterleaver is to write the possible 1512 24-bit words into a ram using one address sequence, and to read them using a different address sequence. this means there is a delay of one cofdm symbol between the input and the output. in the 8 k case, there are 6048 (out of a total of 6817) cofdm carriers that convey data; thus, the L64780 provides a 6048 by 24-bit ram. 2.13 bit deinterleaver in the presence of multipath or interference, some cofdm carriers convey data less ruggedly than others. each cofdm carrier supplies either two, four, or six soft decisions; these would be impaired if the carrier they came from were impaired. for optimum operation of the viterbi decoder, it is best if groups of unreliable soft decisions are maximally spaced. the purpose of the bit deinterleaver is to split up unreliable soft decisions caused by a single unreliable cofdm carrier. the symbol deinterleaver separates groups of unreliable cofdm carriers. the bit deinterleaver accepts groups of 3-bit or 4-bit soft decisions generated from the same cofdm carrier from the symbol deinterleaver.
2-18 architectural overview the bit deinterleaver rearranges these groups of soft decisions to separate soft decisions generated from the same carrier. the bit deinterleaver passes these soft decisions to the output interface of the L64780 for external decoding. there are 6-bit deinterleavers, i0 to i5. for qpsk, one cofdm carrier provides two soft decisions: one from the real part, and one from the imaginary part. i0 deinterleaves the soft decision extracted from the real part; i1 deinterleaves the soft decision from the imaginary part. in this case, i2 to i5 are not used. for 16 qam (both hierarchical and nonhierarchical), one cofdm carrier provides four soft decisions: two from the real part, and two from the imaginary part. ten deinterleaves the msb soft decision extracted from the real part; i1 deinterleaves the msb from the imaginary part. i2 deinterleaves the lsb from the real part; i3 deinterleaves the lsb from the imaginary part. in this case, i4 and i5 are not used. for 64 qam (both hierarchical and nonhierarchical), one cofdm carrier provides six soft decisions: three from the real part, three from the imaginary part. i0 deinterleaves the msb soft decision extracted from the real part; i1 deinterleaves the msb from the imaginary part. i2 deinterleaves the csb from the real part; i3 deinterleaves the csb from the imaginary part. i4 deinterleaves the lsb from the real part; i5 deinterleaves the lsb from the imaginary part.
L64780 dvb-t ofdm demodulator 3-1 chapter 3 interfaces this chapter describes the interfaces for the lsi logic L64780 dvb-t cofdm demodulator. it consists of the following sections: section 3.1, output interface, page 3-1 section 3.2, muxin interface, page 3-8 section 3.3, muxout interface, page 3-13 section 3.4, microprocessor interface, page 3-16 3.1 output interface the output interface formats the soft decisions for presentation to the downstream viterbi decoder. the input to this block is a stream of four- bit or 3-bit viterbi soft decisions from the inner bit deinterleaver. the output from this block connects to a viterbi decoder that is external to the L64780. the output from soft decisions is in a format suitable for direct connection to the l64724 or l64705. this block operates differently in nonhierarchical and hierarchical modes, and can have a serial or parallel output format. this blocks operational modes are described in the following subsections. 3.1.1 output format in nonhierarchical mode in nonhierarchical mode, the output format can be serial or parallel.
3-2 interfaces 3.1.1.1 serial output format in serial output mode, the output port of the L64780 is con?gured as shown in figure 3.1 . figure 3.1 output interface in nonhierarchical and serial modes the output interface passes 4-bit or 3-bit soft decisions to the viterbi decoder through the sd0 signal accompanied by the assertion of dvout. all outputs from the output interface are clocked at 54 mhz by clkout54. with a 64 qam constellation, the L64780 extracts six soft decisions from every constellation point at 9 mhz; for example, one soft decision is presented every 54 mhz clock cycle. see figure 3.2 . figure 3.2 nonhierarchical, serial mode, 64 qam constellation every time a set of soft decisions is received from the bit deinterleaver, the dvout signal stays asserted for six 54 mhz clock cycles. the dvout signal is deasserted only during the scattered pilots, unused carriers, or guard interval. 4 sd0 dvout clkout54 L64780 4 sd1 (not used * ) dvout_lp (not used * ) * when not used, the signal is deasserted low. clkout54 sd0[3:0] dvout sd010 sd08 sd09 sd07 sd06 sd05 sd03 sd04 sd02 sd00 sd01
output interface 3-3 for a 16 qam constellation, during which four soft decisions are extracted every 9 mhz, the dvout signal stays asserted over four out of six 54 mhz clock cycles. see figure 3.3 . figure 3.3 nonhierarchical, serial mode, 16 qam constellation for the qpsk constellation, only two soft decisions are extracted every 9 mhz, resulting in dvout being asserted over two out of six 54 mhz clock cycles. see figure 3.4 . figure 3.4 nonhierarchical, serial mode, qpsk constellation 3.1.1.2 parallel output format in this mode, soft decisions are output in parallel, and the output interface of the L64780 is con?gured. see figure 3.5 . figure 3.5 output interface in nonhierarchical and parallel modes the output interface passes two soft decisions to the viterbi decoder in parallel through sd0 and sd1, accompanied by a data valid indicator. clkout54 sd04 sd05 sd06 sd07 sd00 sd01 sd02 sd03 sd0[3:0] dvout clkout54 sd00 sd01 sd02 sd03 sd0[3:0] dvout sd0 dvout clkout54 L64780 sd1 dvout_lp (not used * ) * when not used, the signal is deasserted low. 4 4
3-4 interfaces because soft decisions are presented in parallel in 64 qam, the soft decisions are presented in three consecutive 54 mhz clock cycles over a six 54 mhz clock cycle period ( figure 3.6 ). the dvout signal is deasserted during the scattered pilots, unused carriers, and guard interval. figure 3.6 nonhierarchical, parallel mode, 64 qam constellation when a 16 qam constellation is used, dvout is asserted for two 54 mhz clock cycles in six clock cycles ( figure 3.7 ). when qpsk is used, it is asserted for only one out of six clock cycles ( figure 3.8 ). figure 3.7 nonhierarchical, parallel mode, 16 qam constellation figure 3.8 nonhierarchical, parallel mode, qpsk constellation clkout54 sd00 sd01 sd02 sd10 sd11 sd12 sd03 sd04 sd05 sd13 sd14 sd15 sd0[3:0] sd1[3:0] dvout clkout54 sd00 sd01 sd10 sd11 sd02 sd03 sd12 sd13 sd0[3:0] sd1[3:0] dvout clkout54 sd10 sd01 sd11 sd00 sd0[3:0] sd1[3:0] dvout
output interface 3-5 3.1.2 output format in hierarchical mode the following subsections describe the decoding of high-priority and low-priority data streams in hierarchical mode. 3.1.2.1 decoding of hp and lp streams in hierarchical mode, the output port of the L64780 is con?gured ( figure 3.9 ). the high- and low-priority streams are delivered on sd0 and sd1, respectively. dvout validates the high-priority data stream; dvout_lp validates the low-priority data stream. figure 3.9 output interface in hierarchical and two fecs modes when in 16 qam mode, two soft decisions are transmitted on sd0 and sd1. dvout and dvout_lp stay asserted for two of six 54 mhz clock cycles. see figure 3.10 . figure 3.10 hierarchical, two fec decoders, 16 qam constellation sd0 (high-priority stream) dvout clkout54 L64780 sd1 (low-priority stream) dvout_lp 4 4 clkout54 sd02 sd03 sd12 sd13 sd00 sd01 sd10 sd11 sd0[3:0] sd1[3:0] dvout dvout_lp
3-6 interfaces when in 64 qam mode, two soft decisions are transmitted on sd0 and four soft decisions are transmitted on sd1. the dvout signal stays asserted during two 540 mhz clock cycles over six 54 mhz clock cycles and the dvout_lp signal stays asserted for four of six 54 mhz clock cycles. see figure 3.11 . figure 3.11 hierarchical, two fec decoders, 64 qam constellation 3.1.2.2 decoding only one stream (hp or lp) in this mode, the output port of the L64780 is con?gured ( figure 3.12 ). the dof_hplp signal selects between the hp and lp output streams. the data stream in this output format is the same as for the nonhierarchical case. figure 3.12 output interface in hierarchical and one fec mode clkout54 sd10 sd11 sd12 sd13 sd00 sd01 sd14 sd15 sd16 sd17 sd02 sd03 sd0[3:0] dvout sd1[3:0] dvout_lp sd0 (hp/lp stream) dvout clkout54 L64780 sd1 (not used * ) dvout_lp (not used * ) * when not used, the signal is deasserted low. 4 4
output interface 3-7 when a set of soft decisions is received from the bit deinterleaver block in 16 qam (hp or lp selected) or in 64 qam (only hp selected), two soft decisions are transmitted over sd0. the result is that dvout is asserted for two of six 54 mhz clock cycles. see figure 3.13 . figure 3.13 hierarchical, one fec decoder mode with 16 qam (hp or lp selected) or 64 qam (lp selected only) when a set of soft decisions is received from the bit deinterleaver block, and the dof function is con?gured in 64 qam with the lp data stream selected, four consecutive soft decisions must be transmitted over sd0. thus, dvalidout is asserted for four of six 54 mhz clock cycles. see figure 3.14 . figure 3.14 hierarchical, one fec decoder mode with 64 qam (hp selected only) \ clkout54 sd00 sd01 sd02 sd03 sd0[3:0] dvout clkout54 sd04 sd05 sd06 sd07 sd00 sd01 sd02 sd03 sd0[3:0] dvout
3-8 interfaces 3.2 muxin interface the muxin bus lets you enter data (or test vectors) into the device at speci?c locations, which lets you bypass some front functional blocks and test an internal functional block. impor tant: this interface is used for lsi logic internal testing and is not intended for use in customer production receivers. the muxin bus (muxinbus) is a 27-bit wide bus, multiplexed with the bypass adc bus (digadcin[9:0]). table 3.1 shows the bus mapping. table 3.1 muxinbus mapping clocking data into the chip is very simple because the L64780 offers a clock output (clkmuxin) that automatically has the correct phase and frequency. clkmuxin automatically selects the correct internal clock, depending on the block selected. figure 3.15 shows how to connect external logic that brings the data to the muxinbus. figure 3.15 muxin signals interface muxinbus[26:10] muxinbus[9:0] muxin[16:0] digadcin[9:0] clkmuxin muxinbus[26:0] L64780 clk test_vector data generator 27
muxin interface 3-9 the muxinbus is software controlled and provides six testing possibilities. the control word is muxin_select[2:0], located at address 0x15, mapped on bits 3 to 5. table 3.2 de?nes the muxin_select[2:0] word. table 3.2 muxin conifguration muxin_select[2:0] de?nition 0 normal mode 1 access to timing and ddfs block 2 access to afc block 3 access to fft block 4 access to csi block 5 input to sdi block 6 reserved 7 reserved
3-10 interfaces 3.2.1 access to timing and ddfs blocks when selecting access to the timing and ddfs blocks, the clkmuxin signal is con?gured as an 18 mhz clock (more precisely, four times the low if). the ddfs block is the digital rotator that performs the carrier frequency compensation. the signals on the bus are i and q data (in twos complement format), a start pulse (start), and a data valid signal (dv). these signals are mapped on the muxinbus. see figure 3.16 . in this mode, you can select whether the start pulse comes from the muxinbus or from the timing recovery unit. the start pulse delimits every cofdm symbol. this selection is done through the ddfs_mode bit (address 0x9, bit 1). if ddfs_mode = 0, the start pulse comes from the test bus (test mode); otherwise, the timing block delivers the start pulse. note that this mode could correspond to an external down- converter that feeds the i and q data directly into the timing and dffs blocks. 3.2.2 access to the afc block the afc block performs the estimation of the carrier frequency drift and produces an analog or digital feedback control signal to compensate for this drift. in this mode, the clkmuxin signal is con?gured as a 36 mhz clock (more precisely, eight times the low if). the signals on the bus are i and q data (in twos complement format), a start pulse (start), a data valid (dv) signal, and the cofdm symbol number (s_nb). these signals are mapped on the muxinbus. see figure 3.17 . figure 3.16 timing and ddfs input mapping 26 25 24 23 21 20 11 10 9 0 0 start dv 0 q[9:0] 0 i[9:0] figure 3.17 afc input mapping 26 25 24 23 22 21 20 11 10 9 0 0 start dv s_nb 0 q[9:0] 0 i[9:0]
muxin interface 3-11 in this mode, you can select whether the cofdm symbol number comes from the tps informations (frame number) or from the muxinbus (s_nb). this selection is done through the afc_mode bit (address 0x5, bit 6). if afc_mode = 0, the cofdm symbol number comes from the muxinbus (s_nb) or full muxin mode; otherwise, it comes from the tps register (partial muxin mode). 3.2.3 access to the fft block in this mode, the clkmuxin signal is con?gured as a 36 mhz clock (more precisely, eight times the low if). the signals on the bus are i and q data (in twos complement format) and a start pulse (start). these signals are mapped on the muxinbus. see figure 3.18 . in this mode, the L64780 can be used as a stand-alone fft processor in forward mode (fft_dir = 0) or in inverse mode (fft_dir = 1). the fft_dir register is located at address 0x11, bit 2. 3.2.4 access to the csi block the csi block performs the channel state information (csi) processing, which builds the soft decisions for the viterbi decoder using a priori information from the channel equalizer (ce). in this mode, clkmuxin is con?gured as an 18 mhz clock (more precisely: four times the low if). the signals on the bus are i and q data (in twos complement format), a start pulse (start), a data valid (dv) signal, the cofdm symbol number (s_nb), and a marker (or data valid) on scattered pilots (dvsp). these signals are mapped on the muxinbus. see figure 3.19 . figure 3.18 fft input mapping 26 25 24 21 20 11 10 9 0 0 start 0 q[9:0] 0 i[9:0] figure 3.19 csi input mapping 26 25 24 23 22 21 11 10 0 dvsp start dv s_nb q[10:0] i[10:0]
3-12 interfaces 3.2.5 access to the sdi block the sdi block performs symbol deinterleaving (sdi) as speci?ed in the etsi speci?cation. in this mode, the clkmuxin signal is con?gured as an 18 mhz clock (more precisely, four times the low if). the signals on the 24-bit data bus (d) contain up to six soft decisions, up to four bits per soft decision, a start pulse (start), a data valid (dv) signal, and the symbol parity (s_p). an odd symbol number is marked by s_p = 1; even symbol numbers are marked by s_p = 0. these signals are mapped on the muxinbus. see figure 3.20 . the data bus (d) is mapped in 3-bit and 4-bit soft decision modes, as shown in figure 3.21 and figure 3.22 , respectively. the msb is at the highest weight position. note that x means reserved. figure 3.20 sdi input mappings 26 25 24 23 0 s_p start dv d[23:0] figure 3.21 d[23:0] bus mapping in three-bit soft decision 23 21 20 19 17 16 15 13 12 11 9 8 7 5 4 3 1 0 qspk i x qpsk q x 16 qam i x 16 qam q x 64 qam i x 64 qam q x figure 3.22 d[23:0] bus mapping in four-bit soft decision 23 20 19 16 15 12 11 8 7 4 3 0 qspk i qpsk q 16 qam i 16 qam q 64 qam i 64 qam q
muxout interface 3-13 3.3 muxout interface the muxout bus lets you probe any point in the device while receiving a transport stream (ts). impor tant: this interface is used for lsi logic internal test purposes and is not intended for customer production receivers. muxoutbus is 27 bits wide. for each probed point, data and control signals are available on this bus (including the clock). the clock has the same aspect ratio as clkmuxin; it is not a 50% duty cycle type. software controls the muxoutbus, which provides ?ve test possibilities. the control word is muxout_select[2:0], located at address 0x15 (bits 2 to 0). table 3.3 de?ne the muxout_select word. note that the muxout bus can be 3-stated by asserting the mux_ctrl bit (bit 3 of the mode register address line), at address 0x19. the bus is active when mux_ctrl is set to 0. table 3.3 muxout_select word de?nition muxin_select[2:0] de?nition 0 ddfs output 2 afc output 3 ce output 4 csi output 5 adc output 6 reserved 7 reserved
3-14 interfaces 3.3.1 ddfs output the ddfs output lets you probe signals after carrier frequency compensation and prior to fft processing. the signals are i and q data (in twos complement format), a start pulse that delimits the cofdm symbols (start), a data valid (dv) signal that accompanies valid data, and an 18 mhz clock. these signals are mapped on the muxoutbus. see figure 3.23 . 3.3.2 fft output the fft output lets you probe data prior to common phase error (cpe) correction and channel equalization (ce). the signals are i and q data (in twos complement format), a start pulse that delimits the cofdm symbols (start), a data valid (dv) signal that accompanies valid data, and a 36 mhz clock. these signals are mapped on the muxoutbus. see figure 3.24 . 3.3.3 afc output the afc output lets you probe data after common phase error (cpe) correction and prior to channel equalization (ce). the signals are i and q data (in twos complement format), a start pulse that delimits the cofdm symbols (start), a data valid (dv) signal that accompanies valid data, and a 36 mhz clock. these signals are mapped on the muxoutbus. see figure 3.25 . figure 3.23 ddfs output mapping 26 25 24 23 22 21 12 11 10 9 0 18 mhz clk start dv 0 q[9:0] 0 i[9:0] figure 3.24 fft output mapping 26 25 24 23 22 21 12 11 10 9 0 36 mhz clk start dv 0 q[9:0] 0 i[9:0] figure 3.25 afc output mappings 26 25 24 23 12 11 0 36 mhz clk start dv q[11:0] i[11:0]
muxout interface 3-15 3.3.4 channel equalizer (ce) output the channel equalizer (ce) output lets you probe data after channel equalization or the frequency response of the channel. after channel equalization, you can display the constellation by feeding i and q data into two dacs. for constellation display purposes, the dacs require only 8-bit resolution. the signals at this point are i and q data in twos complement format, a start pulse that delimits the cofdm symbols (start), a data valid (dv) signal that accompanies valid data, and a 36 mhz clock. these signals are mapped on the muxoutbus. see figure 3.26 . the i and q data available on the bus represent either the equalized data or frequency response of the channel depending upon the ce_select bit (address 0x11, bit 3). when ce_select = 0, equalized data are present on the muxout bus; otherwise, the muxout bus contains the channel response in the frequency domain. 3.3.5 csi output the csi output provides an averaged measure per carrier on the con?dence to be placed on the hard decision. the signals present at this point are the degree of con?dence (csi), a start pulse that delimits the cofdm symbols (start), a data valid (dv) signal that accompanies valid data, and an 18 mhz clock. these signals are mapped on the muxoutbus. see figure 3.27 . a high value on the csi bus indicates a low level of con?dence, and vice- versa. the csi word is nonsigned data, which can be used to drive a bar graph representing the quality of reception in a channel. figure 3.26 ce output mappings 26 25 24 23 12 11 0 36 mhz clk start dv q[11:0] i[11:0] figure 3.27 csi output mappings 26 25 24 23 11 10 0 18 mhz clk start dv 0 csi[10:0]
3-16 interfaces 3.3.6 adc output the adc output lets you probe the internal adc. the signals are the digitized input samples (adc) and the 18 mhz clock. these signals, which are in twos complement format, are mapped on the muxoutbus. see figure 3.28 . 3.4 microprocessor interface the microprocessor interface operates in serial mode. impor tant: a parallel mode interface is provided for test purposes. this interface is used for lsi logic internal testing and is not intended for use in customer production receivers. the serial bus mode interface is a serial interface operating in slave mode. its protocol is compatible with i 2 c speci?cations. for a more detailed description of the serial bus, see appendix a . the p_s input signal selects either the serial or parallel mode. table 3.4 summarizes the different modes. when in serial interface mode, d0 is used as a serial data signal, and a0 is used as a serial clock signal. d[7:1] are used to set the serial bus slave address. when using the serial bus, d[7:1] must be hardwired to set the appropriate device slave address. figure 3.28 adc output mapping 26 25 8 7 0 18 mhz clk 0 adc[7:0] table 3.4 mode selection using the p_s input signal p_s mode notes low parallel lsi internal use only high serial L64780 serial interface
L64780 dvb-t ofdm demodulator 4-1 chapter 4 register descriptions this chapter provides an overview of the L64780 register space and gives a detailed description of its registers. this chapter consists of the following sections: section 4.1, memory map, page 4-2 section 4.2, interrupt registers, page 4-7 section 4.3, tps registers, page 4-11 section 4.4, parameter registers, page 4-16 section 4.5, mux register address line 0x15, page 4-32 section 4.6, performance monitoring registers address line 0x16, page 4-34 section 4.7, mode register address line 0x19, page 4-36 section 4.8, 3-wires register address line 0x1a, page 4-38
4-2 register descriptions 4.1 memory map table 4.1 lists all L64780 registers and provides the dttv demodulator internal memory map. a description of each of these registers groups is provided in the following sections. table 4.1 L64780 registers and internal memory map space address register name register width (bits) type 1 0x00 interrupt register 2 r 0x01 interrupt mask register 2 r/w 0x02 tps register 1 4 r/w 0x03 tps register 2 6 r/w 0x04 tps register 3 7 r/w 0x05 parameters register 1 8 r/w 0x06 parameters register 2 8 r/w 0x07 parameters register 3 8 r/w 0x08 parameters register 4 8 r/w
memory map 4-3 figure 4.1 through figure 4.3 give a graphical view of the register address space. shaded parts in these ?gures denote reserved bits. 2 0x09 parameters register 5 8 r/w 0x0a parameters register 6 8 r/w 0x0b parameters register 7 8 r/w 0x0c parameters register 8 8 r/w 0x0d parameters register 9 8 r/w 0x0e parameters register 10 8 r/w 0x0f parameters register 11 8 r/w 0x10 parameters register 12 8 r/w 0x11 parameters register 13 8 r/w 0x12 parameters register 14 3 r/w 0x13 parameters register 15 6 r/w 0x14 parameters register 16 6 r/w 3 0x15 mux register 6 r/w 0x16 performance monitoring register 1 6 r/w 0x17 performance monitoring register 2 8r 0x18 performance monitoring register 3 8r 0x19 mode register 6 r/w 0x1a 3 wires register 6 rw table 4.1 L64780 registers and internal memory map (cont.) space address register name register width (bits) type
4-4 register descriptions figure 4.1 graphical view of the L64780 register address space 1 0 1 2 3 4 5 6 7 parameter registers sync change interrupt register interrupt mask register 1 tps registers 10 10 0 21 0 10 afc polarity afc sensitivity d dress 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 afc stall afc fine 10 2 afc_init_freq [msb] 3 4 5 6 7 afc mode afc clipping mode tps into change sync change tps into change 10 2 3 4 5 6 7 afc_init_freq [csb] afc_init_freq [lsb] 10 2 10 2 3 4 5 6 7 guard fft mode frame number hierarchy info hp code rate lp code rate 10 2 10 2 qam type
memory map 4-5 figure 4.2 graphical view of the L64780 register address space 2 0 1 2 3 4 5 6 7 parameter registers address 0x0a adc on chip ddfs mode agc polarity 10 2 3 4 5 6 7 tim polarity 0x0b 0x0c 0x0d 1 0x0e ce select tempo type 0x0f csi out format 10 2 3 4 5 10 2 3 4 5 0x10 0x11 ddfs disable fft direction 0x12 10 2 3 4 5 agc disable 0x13 0x14 soft decision width disable tim stall 0x09 r2c si adc format cpe disable ce disable disable ets 0 0 1 2 2 0 1 21 2 sdi bdi disable lp_offset hp_offset format dof out agc gain tim iirgain agc target[msb] tim_loop_p agc target[lsb] 10 2 3 4 5 6 7 10 2 3 4 5 6 7 tim_loop_i timing offset position[lsb] timing offset position[msb] timing clk init [lsb] csi iirate fft gain setting timing clk init [msb]
4-6 register descriptions figure 4.3 graphical view of the L64780 register address space 3 0 1 2 3 4 5 6 7 10 2 3 4 5 6 7 performance monitoring registers address freq ok tps ok frame sync ok sync ok 0x16 0x17 0x18 0x19 mode register change mode auto mode enable 0x1a soft reset 10 2 10 2 mux register 3 wires register mux sd ctrl ctrl 0x15 clock wires3 ctrl odrain ctrl tim muxout select muxin select sync ok average channel state information indication peak channel state information indication 10 2 3 4 5 6 7 10 2 0 1 2 wires3_out wires3_in sync start tim sync ok
interrupt registers 4-7 4.2 interrupt registers the dttv demodulator generates interrupts based on events in speci?c functional blocks of the chip. these events are reported to the interrupt register. two types of events might be of interest to an external microcontroller: events relating to severe impairments. the external microcontroller must evaluate the severity of these events and take the necessary corrective action. events relating to changes in the operation of the dttv demodulator. these occur during normal operation and are made available to the external microcontroller for monitoring. the interrupt register at address 0x00 provides the microprocessor with events on the dttv demodulator that can cause an internal interrupt. this read-only register contains a bitmap indicating which events took place. it is associated with the interrupt mask register. 4.2.1 address line 0x00 res reserved [7:2] these bits are reserved. sync_change synchronization change interrupt r 1 this bit indicates if one or more aspects of the dttv demodulator synchronization have changed. the initial condition for the sync_change bit is 0 (no interrupt). if this bit is set to 1, an interrupt is generated. 7210 0x00 res sync_change tps_info_change
4-8 register descriptions the sync change event is visible through the signal sync change (see section 4.6, performance monitor- ing registers address line 0x16 ) and occurs when at least one of the following synchronizations has changed during the demodulation: the frame_sync_ok bit is set to 1 when the frame synchronization is reached and reset to 0 when the frame synchronization is lost. the frame_sync_ok bit is visible through the performance monitoring register. the freq_sync_ok bit is set to 1 when the demodu- lator is frequency locked and reset to 0 when the fre- quency synchronization is not yet reached or lost. the freq_sync_ok bit is visible through performance monitoring register 1. the start_sync_ok bit is set to 1 when the timing block has properly determined the start of the fft; it is reset to 0 when this is lost. start_sync_ok bit is visible through performance monitoring register 1. the clock_sync_ok bit is set to 1 when the sampling frequency is properly locked; it is reset to 0 when sync is not reached. clock_sync_ok is visible through per- formance monitoring register 1. the tps_sync_ok bit is set to 1 when the tps frame is error free; it is reset to 0 when the frame is corrupted. the tps_sync_ok bit is visible through performance monitoring register 1. tps_info_change tps change interrupt r 0 a valid tps structure has been received that differs from the current mode of the dttv demodulator. this interrupt does not occur if the only change is in the frame number. the tps_info_change bit is initially reset to 0 (no interrupt). if this bit is set to 1, an interrupt is generated. the tps_info_change bit is set to 1 only when the received error-free (bch-correct) tps is different from the last tps information stored in the tps registers. this bit is only reset by a microprocessor read access. the tps_info_change bit is evaluated every cofdm frame, and it is visible through the tps_info_change signal (see section 4.3, tps registers ).
interrupt registers 4-9 4.2.2 interrupt mask register, address line 0x01 the microprocessor can select between a polling or interrupt driven approach by programming the interrupt mask register. only when the bit in the interrupt mask register associated with the event bit in the interrupt register is set to 1 is the interrupt for this event is enabled; otherwise, polling is selected. any interrupt-related events reported in the interrupt register lead to the assertion of the intn signal (active low). on receiving an interrupt signal, the microcontroller is expected to read the interrupt register to identify the cause(s) of this interrupt. the microcontroller thereby resets all interrupt events in the interrupt register; this remains in effect until a new interrupt (tps info change or sync change) occurs. to disable permanently the interrupt mechanism, reset the interrupt mask register. figure 4.4 shows an implementation of the interrupt generation. figure 4.4 interrupt generation event i mask i from other interrupts int and or
4-10 register descriptions note that a read access to address 0 resets the interrupt register. but it does not mask new interrupts that arise at the time the host reads the interrupt register; thus, when the host reads the interrupt register, each interrupt is either reset, or set again if a new interrupt occurs. res reserved [7:2] these bits are reserved. sync_change _mask synchronization change interrupt mask r/w 1 this bit enables or disables the generation of an interrupt if one or more aspects of the dttv demodulator synchronization have changed. if this bit is 0, the interrupt is masked; if the bit is 1, the interrupt is enabled. the initial condition for this bit is 0. tps_info_change_mask tps change interrupt mask r/w 0 this bit enables or disables the generation of the interrupt for the tps_info_change bit. if this bit is 0, the interrupt is masked; if the bit is 1, the interrupt is enabled. the initial condition for this bit is 0. 721 0 0x01 res sync_change_mask tps_info_change_ mask
tps registers 4-11 4.3 tps registers these registers have two functions, depending on whether they are read from, or written to. if they are read from, they indicate that the contents of the last tps structure were correctly received. if they are written to, they set the next mode of operation of the dttv demodulator. the mode change does not take effect until the change_mode command is issued (by setting the change_mode bit in the mode register). the meaning of the bits contained in the tps are described in the etsi speci?cation. 4.3.1 address line 0x02 res reserved [7:4] these bits are reserved. fftmode cofdm transmission mode r/w [3:2] when this register is read, these bits provide the last value received by the channel, using the tps signalling information. when the register is written, these bits store the next cofdm transmission mode value that the system uses. the values are: the initial condition for the fftmode is 0b00 (2k). 743210 0x02 res fft mode guard fftmode[1:0] de?nition 00 2 k mode 01 8 k mode 10 unused 11 unused
4-12 register descriptions guard guard interval r/w [1:0] when this register is read, the guard interval provides the last value received by the channel, using the tps sig- nalling information. when this register is written, guard [1:0] stores the next guard value that the system uses. the values are: the initial condition for the guard interval is 0b00 (1/32). 4.3.2 address line 0x03 res reserved [7:6] these bits are reserved. lp_code_rate viterbi low-priority code rate r/w [5:3] when this register is read, these bits provide the last value received by the channel, using the tps signalling information. guard[1:0] de?nition 00 1/32 guard interval 01 1/16 guard interval 10 1/8 guard interval 11 1/4 guard interval 765 32 0 0x03 res lp_code_rate hp_code_rate
tps registers 4-13 when this register is written, these bits store the next viterbi code rate for the low-priority stream value that the system uses. the values are: the initial condition for the lp_code_rate is 0b000 (1/2). hp_code_rate viterbi high-priority code rate r/w [2:0] when this register is read, these bits provide the last value received by the channel, using the tps signalling information. when this register is written, these bits store the next viterbi code rate for the high-priority stream value that the system uses. the values are: the initial condition for these bits is 0b001 (2/3). lp_code_rate[2:0] de?nition 0 0 0 1/2 code rate 0 0 1 2/3 code rate 0 1 0 3/4 code rate 0 1 1 5/6 code rate 1 0 0 7/8 code rate 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved hp_code_rate[2:0] de?nition 000 1/2 code rate 001 2/3 code rate 010 3/4 code rate 011 5/6 code rate 100 7/8 code rate 101 reserved 110 reserved 111 reserved
4-14 register descriptions 4.3.3 address line 0x04 res reserved 7 this bit is reserved. frame_nb cofdm frame number r [6:5] when this register is read, these bits provide the last value received by the channel, using the tps signalling information. the values are: the initial condition for the frame_nb is 0b00 (frame 0). internally, there are three tps registers: the ?rst (0x02, the active tps register) contains the current mode of the dttv demodulator. the second (the next tps register, 0x03) is written by writing to the tps register in the register map. when the change mode command is issued, the next tps register is copied into the active tps register, and this becomes the current mode of the demodulator. the third register (the received tps register, 0x04) contains a copy of the last valid tps that was received in the input signal. this register can be read by reading from the tps register in the register map. if the auto_mode_enable bit is set, then every time a valid tps is received and a super-frame boundary is detected, the demodulator copies the contents of the received tps register into the active tps register (and changes the current mode of the dttv receiver if the received tps changes). if the received tps (stored in the received tps register) and the current mode of the dttv demodulator (held in 7654 210 0x04 res frame_nb hierarchy qamtype frame_nb[1:0] de?nition 0 0 frame 0 0 1 frame 1 1 0 frame 2 1 1 frame 3
tps registers 4-15 the active tps register) differ, the tps_info_change bit is set to 1 for one clk18 clock cycle. when the tps_info_change interrupt is enabled and this event occurs, the dttv demodulator generates an interrupt to the external microcontroller. the rule for the tps_info_change applies to all tps data bits except for the frame number. hierarchy cofdm nonuniform constellation ratio r/w [4:2] when this register is read, these bits provide the last value received by the channel, using the tps signalling information. when this register is written, these bits store the next constellation expansion ratio that the system uses. the values are: the initial condition for the hierarchy is 0b000 (nonhierarchical). hierarchy[2:0] de?nition 000 nonhierarchical 001 010 011 100 reserved 101 reserved 110 reserved 111 reserved a 1 = a 2 = a 4 =
4-16 register descriptions qamtype constellation type r/w [1:0] when this register is read, these bits provide the last value received by the channel, using the tps signalling information. when this register is written to, these bits store the next constellation type value that the system uses. the values are: the initial condition for the qamtype is 0b10 ( 64 qam). 4.4 parameter registers the parameter registers contain con?guration information. if the registers are read, they indicate the current parameter value. these parameter registers are only con?gurable through the microprocessor. 4.4.1 address line 0x05 afc_clipping afc loop bandwidth limiter r/w 7 this bit selects the combination method between the fine algorithm part and the coarse algorithm part. when using method i (afc_clipping = 0), the combination is done by adding the two values. when the coarse part is an integer number of carrier spacing, and the fine part is a fraction of the carrier spacing, the result is the exact frequency offset. when using method ii (afc_clipping = 1), the fine part is only considered when the afc coarse value is 0. qamtype[1:0] de?nition 00 qpsk 01 16 qam 10 64 qam 11 reserved 765432 0 0x05 afc_ clipping afc_mode afc_fine _mode afc_stall afc_pol afc_sensitivity
parameter registers 4-17 if not, the value applied to the tuner oscillator (via the sigma-delta) is either +1 or - 1. this limits the bandwidth of the system. the initial condition for the afc_clipping bit is 1, which is method ii. afc_mode afc muxin mode r/w 6 when the muxin bus is connected to the afc, this bit determines if the symbol number is coming from the obc (partial muxin mode), as in normal functional mode, or coming from the muxin bus itself (full muxin mode). if this bit is 0, the symbol number is coming from the full muxin mode; if this bit is 1, the symbol number is coming from the partial muxin mode. the initial condition for the afc_mode is 0, the full muxin mode. however, this has no effect if the default mode of afc_muxin is 0 (which means that the afc is taking its symbol number from the obc no matter what the value of afc_mode is). see the de?nition of the muxin register for more information. afc_fine_mode afc fine algorithm mode r/w 5 this bit determines if the afc fine algorithm performs a weighted mean. if the weighted mean mode is chosen (this bit is 0), the afc algorithm performs a weighted mean on the signal measurements to perform its fine afc calculation. if the unweighted mean mode is chosen (this bit is 1), the afc algorithm does not perform a weighted mean on the signal measurements to perform its fine afc calculation. the initial condition for this bit is 0, the weighted mean mode. afc_stall afc loop updating freeze r/w 4 this bit determines if the afc loop is working or frozen. if the loop is working (0), the integrator inside the L64780 updates its value from time to time.
4-18 register descriptions if the loop is stalled (1), the integrator inside the L64780 keeps its internal value constant, enabling you to set the frequency offset by means of software (using afc_init_freq). the initial condition for the afc_stall is 0, the normal working mode. afc_pol afc vco polarity r/w 3 these bits determine the polarity of the external vco. if the polarity is positive (this bit is 0), the output frequency of the external down-converter must increase with increasing voltage from the afcout pin. if the polarity is negative (this bit is 1), the output frequency of the external down-converter must decrease with increasing voltage from the afcout pin. the initial condition for the afc_pol is 0 (positive). afc_sensitivity afc loop gain r/w [2:0] these bits adjust the afc gain of the loop filter. the value is set according to the sensitivity of the afc input of the external down-converter. the values in digital afc loop mode are: the initial condition for these bits is 0b110, or . afc_sensitivity[2:0] de?nition 000 001 010 011 100 101 110 111 k sens 1.52 5 C 10 ? k sens 3 5 C 10 ? k sens 6 5 C 10 ? k sens 1.22 4 C 10 ? k sens 2.44 4 C 10 ? k sens 4.88 4 C 10 ? k sens 9.8 4 C 10 ? k sens 1.95 3 C 10 ? k sens 9.8 4 C 10 ?
parameter registers 4-19 the values in analog afc loop mode are: the initial condition for these bits is 0b110, or . 4.4.2 address lines 0x06, 0x07, 0x08 afc_init_frq afc initial frequency offset r/w [7:0] these three 8-bit registers select the initial frequency offset that is directed towards the tuner or the ddfs block. when these registers are read, the resultant value represents the actual frequency offset (for example, the content of the integrator) recovered by the system. when this register is written, the resultant value rein- itializes the integrator value. three obc accesses are necessary to update these registers; thus, you should ?rst stall the integrator by setting afc_stall to 1, then update the values. you can reactivate the integrator by resetting afc_stall to 0. the initial condition for these registers is 0. afc_sensitivity[2:0] de?nition 000 001 010 011 100 101 110 111 k sens 2.44 4 C 10 ? k sens 4.88 4 C 10 ? k sens 9.8 4 C 10 ? k sens 1.95 3 C 10 ? k sens 3.9 3 C 10 ? k sens 7.8 3 C 10 ? k sens 1.56 2 C 10 ? k sens 3.1 2 C 10 ? k sens 1.56 2 C 10 ? 70 0x06 afc_init_frq_lsb 0x07 afc_init_frq_csb 0x08 afc_init_frq_msb
4-20 register descriptions 4.4.3 address line 0x09 softbit soft decision number of bits r/w 7 this bit determines if a 3-bit (0) or a 4-bit (1) soft decision is used. the initial condition for this bit is 1. bdi_disable bdi disable r/w 6 if this bit is 1, the bit deinterleaver is disabled; if this bit is 1, the bit deinterleaver is enabled. the initial condition for this bit is 0, the normal operational mode. sdi_disable sdi disable r/w 5 if this bit is 1, the symbol deinterleaver is disabled; if this bit is 0, the symbol deinterleaver is enabled. the initial condition for this bit is 0, the normal operational mode. dof_output_format chip output format r/w [4:3] these bits select the output format of the L64780 towards the fec decoder chip. the different formats are described in section 3.4, microprocessor interface. there are three modes: when in nonhierarchical mode, two submodes are provided: serial and parallel. in serial mode, data is presented only on sd0. in parallel mode, data is pre- sented on sd0 and sd1. when in hierarchical mode with only one fec chip, either the hp stream or the lp stream is presented. 76543210 0x09 softbit bdi_ disable sdi_ disable dof_output_ format ddfs_ disable ddfs_ mode adcon
parameter registers 4-21 when in hierarchical mode with two fec chips, hp and lp streams are presented on sd0 and sd1, respectively. the initial condition for these bits is 0b00. ddfs_disable ddfs disable r/w 2 this bit determines if the ddfs performs the baseband correction (0) or not (1). the initial condition for the ddfs_disable is the normal operational mode (0). ddfs_mode ddfs start pulse selector r/w 1 if this bit is 0, the ddfs block gets its start pulse (pulse delimiting every cofdm symbol) from the timing recovery unit block; if this bit is 1, the ddfs block gets its start pulse from the muxin block. the initial condition value for the ddfs_mode bit is 0. the ddfs block can operate in four modes, as listed in table 4.2 . hierarchical dof_output_ format[1:0] de?nition no x 0 serial mode no x 1 parallel mode yes 0 0 hp stream over sd0, 1 fec mode yes 1 0 lp stream over sd0, 1 fec mode yes x 1 hp over sd0, lp over sd1, two fec mode table 4.2 ddfs block modes ddfs mode ddfs muxin ddfs disable functional mode x 0 0 normal 0 1 0 test 1 1 0 down-converter off-chip x x 1 disable mode
4-22 register descriptions when in normal mode, the L64780 receives a real signal in the intermediate frequency (about 4.5 mhz), and the r2c block performs the baseband conversion. in this mode, the ddfs block receives a complex baseband signal directly from the r2c block and takes the ddfs_xin, ddfs_yin, and ddfs_dvin signals and the symbol synchronization ddfs_startin signal from the timing synchronization (tim) block. in down-converter off-chip mode, the baseband conversion is done by the tuner, but the cofdm symbol synchronization signal is still provided by the tim block. in this mode, the ddfs block takes the ddfs_xoff, ddfs_yoff, and ddfs_dvoff signals from the off- chip interface, whereas the symbol synchronization ddfs_startin signal comes from the tim block (see section 3.2.1, access to timing and ddfs blocks, page 3-10 , for the ddfs_xoff, ddfs_yoff, and ddfs_dvoff signals mapping into the muxin bus). when in test mode, the ddfs block receives the baseband complex data and the symbol synchronization from the off-chip interface. in this mode, the ddfs_xoff, ddfs_yoff, ddfs_dvoff, and ddfs_startoff signals come from the off-chip interface. (see section 3.2.1, access to timing and ddfs blocks, page 3-10 , for the ddfs_xoff, ddfs_yoff, and ddfs_dvoff and ddfs_startoff signals mapping into the muxin bus.) in disable mode, only the ddfs_xin, ddfs_yin, ddfs_dvin, and ddfs_startin signals are used; no frequency shift is applied to the incoming complex data, but the data processing time latency must be preserved. adcon adc selector r/w 0 this bit determines if the L64780 uses the 8-bit on-chip (1), or the external 10-bit (0) adc. the initial condition for the adcon is 0, the external 10-bit adc.
parameter registers 4-23 4.4.4 address line 0x0a agc_target_lsb agc target rms value (lsb) r/w [7:5] these bits select the lsbs of the target rms value of the agc loop (see section 2.3.1, agc target rms value ). the initial condition for these bits is 0b100. agc_disable agc disable r/w 4 this bit determines if the agc is disabled (1) or not (0). the initial condition for the agc_disable bit is 0, normal operational mode. agc_pol agc loop polarity r/w 3 this bit selects the polarity of the external agc loop. if the polarity is positive (this bit is 0), the gain of the external down-converter must increase with increasing voltage from the agcout pin. if the polarity is negative (this bit is 1), the gain of the external down-converter must decrease with increasing voltage from the agcout pin. the initial condition for the agc_pol is 1, negative. 754320 0x0a agc_target_lsb agc_disable agc_pol agc_gain
4-24 register descriptions agc_gain agc loop gain r/w [2:0] these bits adjust the agc gain of the loop filter. the value is set according to the sensitivity of the agc loop. the values are: the initial condition for these bits is 0b011, . 4.4.5 address line 0x0b adc_format format of adc output r/w 7 this bit determines if the adc outputs its values in twos complement (1) or in binary offset format (0). the initial condition for the adc_format bit is 0, binary offset. r2c_si cofdm spectrum inversion r/w 6 during the up-conversion and the following down- conversion, the cofdm spectrum can be inverted, depending on the equipment used. this bit determines if the cofdm signal should be spectrally inverted (1) or not (0). the initial condition for the r2c_si bit is 0, normal operation. this spectrum inversion changes the sign of the sine function (negative for 0, positive for 1). agc_gain[2:0] de?nition 000 001 010 011 100 101 110 111 k s 3.9 3 C 10 ? k s 9.8 4 C 10 ? k s 2.4 4 C 10 ? k s 6.1 5 C 10 ? k s 1.5 5 C 10 ? k s 3.8 6 C 10 ? k s 9.5 7 C 10 ? k s 2.4 7 C 10 ? k s 6.1 5 C 10 ? 765 0 0x0b adc_format r2c_si agc_target_msb
parameter registers 4-25 agc_target_msb agc target rms value (msb) r/w [5:0] these bits select the msbs of the target rms value of the agc loop (see section 2.3.1, agc target rms value ). the initial condition for these bits is 0x0e. 4.4.6 address line 0x0c tim_loop_i timing gain loop 2 r/w [7:5] these bits adjust the timing gain of the loop filter. the value is set according to the sensitivity of the vxco loop. the initial condition for the tim_loop_i is ob011 (gain 3) . 754210 0x0c tim_loop_i tim_loop_p tim_iirgain tim_loop_i[2:0] de?nition 000 001 010 011 100 101 110 111 k i 0.125 ? k i 3.125 2 C 10 ? k i 7.8 3 C 10 ? k i 1.95 3 C 10 ? k i 4.8 4 C 10 ? k i 1.22 4 C 10 ? k i 3 5 C 10 ? k i 7.63 6 C 10 ? k i 1.95 3 C 10 ?
4-26 register descriptions tim_loop_p timing gain loop 1 r/w [4:2] these bits adjust the timing gain of the loop filter. the value is set according to the sensitivity of the vxco loop. the initial condition for the tim_loop_p is 0b011 (gain 3) . tim_iirgain timing iir filter time constant r/w [1:0] these bits govern the amount of iir filtering done in the timing loop filter. the initial condition for the tim_iirgain is 0b01 (gain 1) . tim_loop_p[2:0] de?nition 000 001 010 011 100 101 110 111 k p 8.0 ? k p 4.0 ? k p 2.0 ? k p 1.0 ? k p 0.5 ? k p 0.25 ? k p 0.125 ? k p 6.25 2 C 10 ? k p 1. 0 ? tim_iirgain[1:0] de?nition 00 01 10 11 a 6.25 2 C 10 ? a 3.125 2 C 10 ? a 1.56 2 C 10 ? a 7.8 3 C 10 ? a 3.125 2 C 10 ?
parameter registers 4-27 4.4.7 address line 0x0d tim_offset_lsb start pulse phase offset (lsb) r/w [7:0] the start pulse is a signal with a periodicity of every fft-mode+guard 9 mhz cycles (in steady state). the tim_offset bits adjust the phase of this signal in the periodic window. the initial condition for the tim_offset_lsb bits is 0x00. 4.4.8 address line 0x0e tim_stall tim loop updating freeze r/w 7 this bit determines if the loop is working (this bit is 0) or stalled (this bit is 1). if the loop is working, the integrator inside the L64780 updates its value. if the loop is stalled, the integrator inside the L64780 keeps its internal value constant, letting you set the vcxo frequency offset by means of the tim_clk_init bits. the initial condition for the tim_stall bit is 0, normal working mode. tim_pol tim vcxo polarity r/w 6 this bit determines the polarity of the external vcxo: if the polarity is positive (this bit is 0), the output frequency of the external vcxo increases with increasing voltage from vcxout. if the polarity is negative (this bit is 1), the output frequency of the external vcxo decreases with increasing voltage from vcxout. the initial condition for the tim_pol is 1, negative polarity. 70 0x0d tim_offset_lsb 765 0 0x0e tim_stall tim_pol tim_offset_msb
4-28 register descriptions tim_offset_msb start pulse phase offset (msb) r/w [5:0] the start pulse is a signal with a periodicity of every fft-mode + guard 9 mhz cycles (in steady state). the tim_offset bits adjust the phase of this signal in the periodic window. the initial condition for these bits is 0x00. 4.4.9 address lines 0x0f, 0x10 tim_clk_init timing initial vcxo offset r/w [7:0] these two registers, tim_clk_init_lsb and tim_clk_init_msb, select the initial vcxo frequency offset that is directed to the external vcxo. when this register is read, its value represents the actual vcxo offset (for example, the content of the integrator) recovered by the system. when this register is written, this value reinitializes the integrator value. two obc accesses are required to update these registers; thus, you should first stall the integrator by setting tim_stall to 1, then update the values. the process can be unfrozen by clearing tim_stall back to 0. the initial condition for these bits is 0x00 (both registers set to 0x00). 70 0x0f tim_clk_init_lsb 0x10 tim_clk_init_msb
parameter registers 4-29 4.4.10 address line 0x11 i cpe_disable common phase error disable r/w 7 this bit determines if the cpe is disabled (1) or not (0). the initial condition for this bit is 0, normal operation. ce_disable ce disable r/w 6 this bit determines if the ce is disabled (1) or not (0). the initial condition for this bit is 0, normal operation. ce_disable_ets ce timing shift disable r/w 5 the channel equalizer emulates a negative echo to ease implementation. if this bit has a value of 1, the negative echo generation is disabled. if this bit is set to 0, the negative echo generation is enabled. the initial condition for this bit is 0, working mode. ce_tempotype ce timing interpolation type r/w 4 this bit selects the mode of operation of the channel equalizer timing interpolation. if this bit is 0, the mode is zero order hold; if this bit is 1, the mode is linear. the initial condition for this bit is 1, linear. ce_select ce muxout selector r/w 3 when muxout is selected to output the channel equalizer value, either the channel response (1) or the equalized data (0) can be output. note that both cases do not affect receiver functionality. the initial condition for this bit is 0, equalized data. fft_dir fft direction r/w 2 this bit determines if the fft is in forward mode (timing to frequency domain, 0) or backward mode (frequency to timing domain, 1). for L64780 normal operational mode, the fft direction is forward. the initial condition for the fft_dir is 0, forward. 76 5 4 3210 0x11 cpe_ disable ce_ disable ce_ disable_ ets ce_tempo- type ce_sel ect fft_dir fft_gain
4-30 register descriptions fft_gain fft clipping and rounding r/w [1:0] this register selects how the fft clips and rounds in case of over?ow. the values are: the initial condition for these bits is 0b10, gain 2. 4.4.11 address line 0x12 res reserved [7:3] these bits are reserved. csi_out_format csi softbits format r/w 2 this bit allows the generation of softbit values either in twos complement (1) or in binary offset (0). the initial condition for this bit is 0, binary offset. csi_iirate csi iir filter gain r/w [1:0] these bits set the iir gain of the channel state information unit. the values are: the initial condition for the csi_iirate is 0b01, gain 1. fft_gain[1:0] de?nition 0 0 gain 0 0 1 gain 1 1 0 gain 2 1 1 gain 3 73210 0x12 res csi_out_ format csi_iirate csi_iirate[1:0] de?nition 0 0 gain 0 0 1 gain 1 1 0 gain 2 1 1 gain 3
parameter registers 4-31 4.4.12 address line 0x13 res reserved [7:6] these bits are reserved. hp_offset csi hp stream quantizer gains r/w [5:0] these bits set the quantizer gain of the channel state information unit for the high-priority stream. the initial value for the hp_offset bits is 0x36. 4.4.13 address line 0x14 res reserved [7:6] these bits are reserved. lp_offset csi lp stream quantizer gains r/w [5:0] these bits set the quantizer gain of the channel state information unit for the low-priority stream. the initial value for the lp_offset is 0x36. 765 0 0x13 res hp_offset 765 0 0x14 res lp_offset
4-32 register descriptions 4.5 mux register address line 0x15 this register brings data to and from speci?c blocks. the muxin register is directly output from the obc and goes to the clock generator block. res reserved [7:6] these bits are reserved. muxin muxin selector r/w [5:3] these bits select the point in the system to be driven through the muxin input pins and the clkmuxin clock to sample the data coming into the L64780. there are six possibilities: the initial value for muxin is 0b000 (no muxin). table 4.3 de?nes how to set the different muxin signals and the muxin clock. 765320 0x15 res muxin muxout muxin de?nition muxin clock 000 normal mode set low 001 muxin inputs to timing and ddfs block 18 mhz 010 muxin inputs to afc block 36 mhz 011 muxin inputs to fft block 36 mhz 100 muxin inputs to csi block 18 mhz 101 muxin inputs to sdi block 18 mhz 110 unused set low 111 unused set low
mux register address line 0x15 4-33 muxout muxout selector r/w [2:0] these bits select the point in the system to be monitored through the output block. there are six possibilities: the initial value for these bits is 0b011, ce output. table 4.3 muxin signal settings and muxin clock muxin tim muxin ddfs muxin afc muxin fft muxin csi muxin sdi muxin muxin clock 000000000setlow 001110000 clk18 010001000 clk36 011000100 clk36 100000010 clk18 101000001 clk18 110000000setlow 111000000setlow muxout[2:0] de?nition 0 0 0 ddfs output presented 0 0 1 fft output presented 0 1 0 afc output presented 0 1 1 ce output presented 1 0 0 csi output presented 1 0 1 afc output presented 1 1 0 unused 1 1 1 unused
4-34 register descriptions 4.6 performance monitoring registers address line 0x16 these registers contain the aggregate statistical and monitoring information available to the obc block. res reserved [7:6] these bits are reserved. frame_sync_ok cofdm frame synchronization r/w 5 if the frame synchronization in the dttv demodulator is correct, this bit is 1 (odfm frame is locked). if this bit is 0, the cofdm frame is unlocked. the initial condition for this bit is 1, locked. tps_sync_ok tps synchronization r/w 4 if the bch code in the tps indicates that the tps is valid, this bit is 1 (tps is locked). if this bit is 0, tps is unlocked. the initial condition for this bit is 1, locked. afc_sync_ok afc synchronization r/w 3 if the frequency synchronization in the dttv demodulator is correct, this bit is 1 (afc locked); otherwise, it is 0 (unlocked). the initial condition for this bit is 1, locked. tim_clk_sync_ok timing synchronization r/w 2 if the sampling frequency synchronization in the dttv demodulator is correct, this bit is 1 (vcxo is locked); otherwise, it is unlocked. the initial condition for this bit is 1, locked. 76 5 4 3 2 1 0 0x16 res frame_ sync_ ok tps_ sync_ ok afc_ sync_ ok tim_clk_ sync_ok tim_ start_ sync_ok sync_ok
performance monitoring registers address line 0x16 4-35 tim_start_sync_ok start pulse synchronization r/w 1 if the start fft window synchronization (start pulse is locked) in the dttv demodulator is correct, this location is 1; otherwise, the start pulse is unlocked. the initial condition for this bit is 1, locked. sync_ok overall chip synchronization r/w 0 if all aspects of the dttv demodulator are synchronized, this bit is 1. if this bit is 0, at least one unit is not locked. the initial condition for this bit is 1, locked. 4.6.1 address line 0x17 csi_average csi reliability average r [7:0] this register indicates the overall reliability of the carriers by making an average (integer number) of the reliability of each carrier. 4.6.2 address line 0x18 csi_peak csi reliability peak r [7:0] this register gives the integer number of carriers when the value of the ?ltered channel state information exceeds a given threshold. if more than 255 carriers exceed this value, then 255 is returned. 70 0x17 csi_average 70 0x18 csi_peak
4-36 register descriptions 4.7 mode register address line 0x19 this register in?uences how the dttv demodulator operates. res reserved 7 this bit is reserved. odrain_ctrl output drain controller r/w 6 this bit allows the 3-wire bus pins to be set in open drain mode. when this bit is 1, the 3-wire output bus is working in open drain (1 => z, 0 => 0). when this bit is 0, the bus is in normal mode. the initial condition for this bit is 1, output drain mode. the wires3_ctrl and odrain_ctrl bits generate the obc_wire3_ctrl[2:0] 3-state control signals, as speci?ed in the following table. wires3_ctrl 3-wire bus 3-state controller r/w 5 when this bit is 1, the 3-wires bus pins are 3-stated. when this bit is 0, the bus pins are in normal mode. the initial condition for this bit is 0, normal mode. 76543210 0x19 res odrain _ctrl wires3 _ctrl sd_ ctrl mux_ ctrl soft_ reset auto_ mode_ enable change _mode obc_wire3_out odrain_ctrl wire3_ctrl out 0000 0100 001z 011z 1001 110z 101z 111z
mode register address line 0x19 4-37 sd_ctrl normal output 3-state controller r/w 4 when this bit is 1, all normal pins are 3-stated. the initial condition for this bit is 0, normal mode. mux_ctrl muxout 3-state controller r/w 3 when this bit is 1, all muxout pins are 3-stated. the initial condition for this bit is 0, normal mode. soft_reset chip soft reset r/w 2 setting this bit enables a hard reset of the L64780 logic (except the obc registers, which keep their values). this allows a proper reset of the chip in any default con?guration (memories are also reset to 0). note that the soft reset must be asserted from the external microcontroller; it is not a pulse. when this bit is 1, soft reset is enabled. when this bit is 0, no soft reset is possible. auto_mode_enable tps auto updating r/w 1 this bit determines if the tps updating is controlled by the external microcontroller, or if the active registers are automatically updated each time new value tps arrive from the broadcaster. if this bit is 1, the current mode (as de?ned by the tps register) of the demodulator is updated whenever a valid tps is received. if this bit is 0, manual con?guration of the tps register is required. the initial condition for this bit is 0, manual update. change_mode tps updating register w 0 when a new mode of operation has been written into the tps register, writing the value 1 into this location causes the demodulator to change mode. see section 4.3, tps registers, page 4-11 for more information.
4-38 register descriptions 4.8 3-wires register address line 0x1a the 3-wires register emulates the 3-wires bus protocol and controls the tuner. it can also be used to emulate a software i 2 c interface towards the tuner. res reserved [7:6] these bits are reserved. wires3_in 3-wires input r/w [5:3] these bits collect the information coming from the 3-wires off-chip inputs. the initial condition for wires3_in is 0x0. wires3_out 3-wires output r/w [2:0] these bits are directly presented off-chip to the control tuner. the initial condition for wires3_out is 0x0. 765 32 0 0x1a res wires3_in wires3_out
L64780 dvb-t ofdm demodulator 5-1 chapter 5 signal descriptions this chapter describes the L64780 signals. these signals are grouped by function. within each group, the signals are described in alphabetical order. this chapter consists of the following sections: section 5.1, overview, page 5-1 section 5.2, microprocessor interface, page 5-3 section 5.3, main signals, page 5-4 section 5.4, sigma-delta outputs, page 5-6 section 5.5, mux signals, page 5-6 section 5.6, 3-wires signals, page 5-7 section 5.7, jtag signals, page 5-7 section 5.8, test pins, page 5-8 section 5.9, asic pins, page 5-8 section 5.10, pll pins, page 5-8 section 5.11, tester pins, page 5-9 5.1 overview figure 5.1 provides the logic symbol for the L64780.
5-2 signal descriptions figure 5.1 L64780 logic symbol d dtackn intn csn a agcout afcout main inputs L64780 dvb-t receiver dvout sd1 sd0 dvout_lp clkout54 main outputs p_s asn vcxout startout sigma-delta outputs 3 wires i/o jt a g pins t ester pins asic pins muxin muxout clkmuxin mux i/o xctr_in xctr_out pll pins read 4 4 27 17 3 3 plltstsel plltstclk pllvss pllvdd pllagnd plllp2 ttn tiddtn procq test0 test1 tck tms tdi tresetn tdo 10 reset digin clk18 avin adcpd adcgvss adcvss adcgvdd adcvdd addvrefp adcvrefn ibias 5 8 microprocessor interf ace
microprocessor interface 5-3 5.2 microprocessor interface this section lists and describes the microprocessor interface signals. note that the parallel interface mode is used for lsi logic internal testing and is not intended for use in customer production receivers. the serial mode interface is used for production systems. a[4:0] address bus i the dttv receiver has a ?ve-bit address bus, a[4:0], that is used with an eight-bit data bus, d[7:0], a read/write strobe, read, an address strobe, asn, and a chip select strobe, csn, to read and write internal registers. the address lines select internal registers. in serial mode, a0 is used as the serial clock, and a[4:1] must be connected to ground. asn address strobe i active low address strobe input. latches the address on the a[4:0] bus on the falling edge. in serial interface mode, asn must be connected to vdd. csn chip select i active low chip select strobe input. during a read cycle, csn must be low to access the on-chip data registers. during a read access, the external controller can latch the data from the dttv receiver with the rising edge of csn. during a write access, csn must go low prior to data being valid from the external controller to the dttv receiver. in serial interface mode, csn must be con- nected to vdd. d[7:0] microprocessor data bus i/o this bidirectional bus is used as an input when data is written to the chip, and as an output when the chip is read. when the L64780 is not being read or written to, the data lines are 3-stated. in serial interface mode, d0 is used as the serial data, and d[7:1] are used for the programmable serial bus interface. dtackn data transaction acknowledge o active low output indicating that the transaction has been completed. when not driven, the line is open-drain 3-stated.
5-4 signal descriptions intn interrupt o the dttv receiver asserts intn when an internal, unmasked interrupt ?ag is set. intn remains asserted as long as the interrupt condition persists and the interrupt ?ag is not masked. when not driven, the line is open- drain 3-stated. p_s microprocessor operation mode i when this signal is low, operation is parallel mode; when high, operation is serial mode. read read strobe i when high, a read operation is selected; when low, a write operation is selected. in serial interface mode, read must be connected to vdd. 5.3 main signals this section lists and describes the main signals input to the L64780 or output to the l64705/l64724. adcgvdd guard vdd for internal adc i must be connected to vdd. adcgvss internal adc guard vss i must be connected to ground. adcpd power-down mode for internal adc i this pin is active high and in normal mode must be con- nected to ground. adcvdd analog vdd for internal adc i must be connected to vdd. adcvrefn internal adc negative reference voltage i when not used, this pin must be connected to ground. adcvrefp internal adc positive reference voltage i when not used, this pin must be connected to ground. adcvss analog vss for internal adc i must be connected to ground. avin analog input for internal adc i for an external adc, this pin must be connected to ground.
main signals 5-5 clk18 18 mhz clock i this is the 18 mhz input clock coming from the external vcxo. clkout54 54 mhz clock o this is the 54 mhz clock output and is used to clock the l64705 or the l64724. digin[9:0] digital inputs i digital inputs in normal mode when a 10-bit off-chip adc is used. digin0 represents the lsb, while digin9 represents the msb. this bus is latched with the clk18 clock. in muxin mode, digin[9:0] represents the 10 lsbs of the 27 muxin bits, with digin[0] mapped to muxin0, and digin9 to muxin9. for an on-chip adc, this bus must be connected to ground. dvout sd0 data valid out o 3-state when asserted high, this signal validates the sd0[3:0] bus. dvout_lp sd1 data valid out o 3-state when asserted high, this signal validates the sd1[3:0] bus. ibias input bias current for internal adc i when not used, this pin must be connected to ground. reset reset i hard reset. this pin is activ e-high. see section table 6.6, reset ac timing parameters, page 6-5 , for the mini- mum and maximum assertion time for a valid res et. sd0[3:0] sd0 bus o 3-state the ?rst 4-bit output bus used to output the high- and low-priority streams. sd1[3:0] sd1 bus o 3-state the second 4-bit output bus used to output the high- and low-priority streams. startout first soft decision mark o 3-state when asserted high, this signal marks the ?rst soft decision of an cofdm symbol to be presented off-chip.
5-6 signal descriptions 5.4 sigma-delta outputs this section lists and describes the output signals to the l64705/l64724. agcout agc output o open drain sigma-delta output of the agc. vcxout o open drain sigma delta output of the vcxout. afcout afc output o open drain sigma delta output of the afcout. 5.5 mux signals this section lists and describes the mux input and output signals. this interface is used for lsi logic internal testing and is not intended for use in customer production receivers. muxin[16:0] muxin bus i pull-down this bus is combined with the 10-bit adcin[9:0] to form a 27-input muxin bus. when not used, this bus must be connected to ground. clkmuxin clock for muxin i clock this pin provides the clock to latch the muxin bus. muxout[26:0] mux test bus o 3-state this 27-input bus is used for testing.
3-wires signals 5-7 5.6 3-wires signals this section lists and describes the 3-wire signals. xctr_out[2:0] tuner control output o 3-state these three output pins are mainly used to control the tuner and are directly controlled through the microprocessor. xctr_in[2:0] tuner control input i these three input pins collect information from the tuner. when not used, these pins must be connected to ground. 5.7 jtag signals this section lists and describes the jtag signals. tck jtag tap clock i pull-up when in normal operating mode, this pin must be connected to vdd. tdi jtag tap test data input i pull-up when in normal operating mode, this pin must be connected to vdd. tdo jtag tap test data output o 3-state jtag tap test data output. tms jtag tap test mode select i pull-up when in normal operating mode, this pin must be connected to vdd. tresetn jtag tap reset i pull-up when in normal operating mode, this pin must be connected to vdd.
5-8 signal descriptions 5.8 test pins this section lists and describes the test signals. test0 test selection 0 i this pin is used for test selection. when in normal operating mode, this pin must be connected to ground. test1 test selection 1 i this pin is used for test selection. when in normal operating mode, this pin must be connected to ground. 5.9 asic pins this section lists and describes the asic signals. ttn i this pin is active low and controls all the output pins. in normal operating mode, it must be connected to vdd. tiddtn i this pin is active high. in normal operating mode, it must be connected to ground. procq o dedicated output for asic characterization. 5.10 pll pins this section lists and describes the pll signals. pllvss ground for internal pll i this signal must be connected to ground. pllvdd vdd for internal pll i this signal must be connected to vdd. pllagnd analog ground for internal pll i this signal must be connected to ground. plllp2 vco voltage control i this signal must be connected to the external ?lter.
tester pins 5-9 5.11 tester pins this section lists and describes the internal tester signals. plltstclk i pin dedicated to internal test purposes. in normal operating mode, this pin must be connected to ground. plltstsel i pin dedicated to internal test purposes. in normal operating mode, this pin must be connected to ground.
5-10 signal descriptions
L64780 dvb-t ofdm demodulator 6-1 chapter 6 speci?cations this chapter describes the electrical speci?cations, power requirements, dc characteristics, and ac timing parameters for the l6780. it consists of the following sections: section 6.1, electrical speci?cations, page 6-1 section 6.2, ac timing, page 6-4 section 6.3, signal speci?cations, page 6-6 section 6.4, pinouts, page 6-11 section 6.5, mechanical drawing, page 6-15 6.1 electrical speci?cations this section speci?es the electrical requirements for L64780. table 6.1 lists the absolute maximum ratings for the L64780. table 6.1 absolute maximum ratings parameter symbol limits 1 1. the ratings in this table are those beyond which permanent device damage is likely to occur. these values should not be used as the limits for normal device operation. unit dc supply voltage v dd - 0.3 to +3.9 v lvttl input voltage v in - 1.0 to v dd + 0.3 v 5 v compatible input voltage v in - 1.0 to 6.5 v dc input current i in 10 ma storage temperature range (plastic) t stg - 40 to +125 c
6-2 speci?cations table 6.2 lists the recommended operating conditions for the L64780. table 6.3 lists the dc characteristics of L64780, which is produced with the lcbg10p process. this is a 0.35-micron drawn gate length cell- based process. characteristics in the table are the same for any device that has a buffer with the listed parameters. table 6.2 recommended operating conditions parameter symbol limits 1 unit dc supply voltage v dd +3.0 to +3.6 v operating ambient temperature range t a 0to+70 c 1. for normal device operation, adhere to the limits in this table. sustained operation of the device at conditions exceeding these values, even if they are within the absolute maximum rating limits, can result in permanent device damage or impaired device reliability. device functionality to stated dc and ac limits is not guaranteed if conditions exceed recommended operating conditions. table 6.3 dc characteristics symbol parameter condition min typ max unit v dd supply voltage 3.0 3.3 3.6 v v il input low voltage v ss - 0.5 0.8 v v ih input high voltage lvttl temp range 2.0 v dd +0.3 v 5-v compatible 2.0 5.5 v v t switching threshold 1.4 2.0 v v t+ schmitt trigger, positive- going threshold 1.7 2.0 v v t - schmitt trigger, negative- going threshold 0.8 1.0 v schmitt trigger, hysteresis 0.6 0.7 v i in input current inputs with pulldown resistors inputs with pullup resistors v in =v dd or v ss v in =v dd v in =v ss - 10 35 -35 1 115 - 115 10 222 - 214 ma ma ma
electrical speci?cations 6-3 v oh output high voltage type b1 type b2 type b4 type b6 type b8 type b12 1 i oh =-1ma 2 i oh =-2ma 3 i oh =-4ma 3 i oh =-6ma 3 i oh =-8ma 3 i oh =-12 ma 3 2.4 2.4 2.4 2.4 2.4 2.4 v dd v dd v dd v dd v dd v dd v v v v v v v ol output low voltage type b1 type b2 type b4 type b6 type b8 type b12 2 i ol =1ma i ol =2ma i ol =4ma i ol =6ma i ol =8ma i ol =12 ma 0.2 0.2 0.2 0.2 0.2 0.2 0.4 0.4 0.4 0.4 0.4 0.4 v v v v v v i oz 3-state output leakage current v oh =v ss or v dd - 10 110 ma i os output short circuit current 3, bt4 v o =v dd v o =v ss 140 - 40 ma ma output short circuit, bt4f v o =v dd v o =v ss 67 - 86 ma ma i dd quiescent supply current v in =v dd or v ss i cc dynamic supply current tbd ma c in input capacitance 4 input and bidirectional buffers 2.5 pf 5-volt compatible 3.0 pf c out output capacitance 5 output buffer 5 2.0 pf 5-volt compatible 3.0 pf 1. requires two output pads. 2. see the interfacing to 5 v signals using g10 ? -p technologies application note for f series out- put buffer i oh values. 3. type b4 output. output short circuit current for other outputs will scale. 4. excluding package capacitance. 5. output using single buffer structure (excluding package). table 6.3 dc characteristics (cont.) symbol parameter condition min typ max unit
6-4 speci?cations 6.2 ac timing the following subsections provide the ac timing for the input data interface and output data interface. 6.2.1 input data interface figure 6.1 shows the waveform timing for the input data interface. figure 6.1 input data ac timing table 6.4 lists the ac timings for the input data interface of the L64780. 2 digadcin clk18 1 4 3 table 6.4 input data ac timing parameters no. parameter description min max unit 1t s input setup time to clk18 6 C ns 2t h input hold time to clk18 C 13 ns 3t pwh clock pulse width high 24.9 C ns 4t cycle clock cycle time 55.5 C ns
ac timing 6-5 6.2.2 output data interface figure 6.2 shows the waveform timing for the output data interface. figure 6.2 output data ac timing table 6.5 lists the ac timing parameters for the output data interface of the L64780. 6.2.3 reset timing figure 6.3 illustrates the reset timing for L64780. table 6.6 lists and describes the output data ac timing parameters. figure 6.3 reset timing . 1 s0[3:0] s1[3:0] startout dvout dvout_lp clkout54 t t = 3/2 * clk18 table 6.5 output data ac timing parameters parameter description min max unit 1t od output delay from clkout54 falling edge C 5.0 ns reset 1 2 table 6.6 reset ac timing parameters parameter description min max unit 1t rwh reset pulse width high 3 C clk18 cycles 2t wk wake-up time (pll acquisition time) 300 C ms
6-6 speci?cations 6.3 signal speci?cations table 6.7 provides a summary of the pin numbers and their associated signals, grouped by function. table 6.7 signal summary list pin pin name description buffer type 5-volt comp- atible drive (ma) type active major i/os 99 clk18 input clock lvttl input yes C 20 reset main reset lvttl input yes high 34 clkout54 clock output to the l64705 or l64724 lvttl output ye s C microprocessor interface 125C9 a[4:0] address bus 1 lvttl input yes pull-down C 109C18 d[7:0] data bus 2 lvttl bidir yes 4 C 108 read read/write selection lvttl input yes pull-up C 107 csn chip select lvttl input yes pull-up low 106 asn address strobe lvttl input yes pull-up low 35 dtackn data acknowledge lvttl output yes 4 3-state low 36 intn interrupt lvttl output yes 4 open drain low 105 p_s serial/parallel mode lvttl input yes C
signal speci?cations 6-7 main input 144C142, 139, 138, 135C133, 131, 130 digin[9:0] digital input in normal mode. testin input otherwise lvttl input yes pull-down C 152 adcpd adc power down analog input yes high 153 adcgvss guard vss supply analog input yes C 154 adcvss analog vss supply analog input yes C 155 adcvrefp positive reference voltage analog input yes C 156 adcvrefn negative reference voltage analog input yes C 157 avin analog input when using the internal adc analog input yes C 158 ibias input bias current analog input yes C 159 adcvdd analog vdd supply analog input yes C 160 adcgvdd guard vdd supply analog input yes C table 6.7 signal summary list (cont.) pin pin name description buffer type 5-volt comp- atible drive (ma) type active
6-8 speci?cations main output 63 dvout sd0 data valid out lvttl output yes 4 3-state C 62 dvout_lp sd1 data valid out lvttl output yes 4 3-state C 61 startout first soft decision mark lvttl output yes 4 3-state C 56C8, 60 sd0[3:0] sd0 bus lvttl output yes 4 3-state C 51C3, 55 sd1[3:0] sd1 bus lvttl output yes 4 3-state C pwm output 42 vcxout vcxout timing loop lvttl output yes 4 open drain C 122 afcout output to the tuner lvttl output yes 4 open drain C 150 agcout output to the agc lvttl output yes 6 open drain C mux in pins 5, 6, 8C 12, 14C 18, 21C 24, 26 muxin[16:0] input mux. combined with digadcin to form 27 input bits lvttl input yes pull-down C 50 clkmuxin clock output use to generate muxin bus lvttl output ye s 4 C table 6.7 signal summary list (cont.) pin pin name description buffer type 5-volt comp- atible drive (ma) type active
signal speci?cations 6-9 mux out 64, 66C69, 71C74, 76C79, 82C85, 87C90, 92C97, muxout[26:0] output mux: mainly for test issues lvttl output yes 4 3-state C 3 wires buffer 37C39 xctr_out[2:0] pins used to control the tuner lvttl output yes 4 3-state C 2C4 xctr_in[2:0] pins used to retrieve informations from tuner lvttl input yes C jtag: test access port (tap) 28 tck jtag tap clock lvttl input yes pull-up C 29 tms jtag tap test mode select lvttl input yes pull-up C 30 tdi jtag tap test data input lvttl input yes pull-up C 33 tdo jtag tap test data output lvttl output yes 4 3-state C 27 tresetn jtag tap reset lvttl input yes pull-up low test pll; scan mode; bist mode 46 test0 test mode selection lvttl input yes C 47 test1 test mode selection lvttl input yes C table 6.7 signal summary list (cont.) pin pin name description buffer type 5-volt comp- atible drive (ma) type active
6-10 speci?cations asic speci?c pins 45 ttn control tn pins of all bidirectional and 3-state outputs lvttl input yes low 140 tiddtn control power down pll, oscillator and disable pull up/pull down lvttl input yes high 147 procq dedicated output of procmon lvttl output ye s C internal pll pins 103 pllvss pll ground analog input yes C 100 pllvdd pll power analog input yes C 102 plllp2 vco control voltage pin, connection to external loop ?lter analog bidir yes C 101 pllagnd pll analog ground analog output ye s C tester pins 145 plltstclk open pll loop lvttl input yes C 146 plltstsel replace pll clk output and feedback loop lvttl input yes high 1. a0 is also used as the i 2 c serial clock. therefore pin a0 is a schmitt buffer. 2. d0 is also used as the i 2 c serial data. therefore, pin d0 is a bidirectional schmitt buffer. table 6.7 signal summary list (cont.) pin pin name description buffer type 5-volt comp- atible drive (ma) type active
pinouts 6-11 6.4 pinouts the following subsections provide a numerical and alphabetic listing of the L64780 pins, as well as a pinout package drawing showing the location of the pins. 6.4.1 pin list table 6.8 numerically lists the L64780 pins and their associated signals.
6-12 speci?cations table 6.8 pin list by number table 6.9 alphabetically lists the L64780 signals and their associated pins. signal pin vdd 1 xctr_in0 2 xctr_in1 3 xctr_in2 4 muxin0 5 muxin1 6 vss2 7 muxin2 8 muxin3 9 muxin4 10 muxin5 11 muxin6 12 vdd 13 muxin7 14 muxin8 15 muxin9 16 muxin10 17 muxin11 18 vss2 19 reset 20 muxin12 21 muxin13 22 muxin14 23 muxin15 24 vdd 25 muxin16 26 tresetn 27 tck 28 tms 29 tdi 30 vss2 31 vss 32 tdo 33 clkout54 34 dtackn 35 intn 36 xctr_out0 37 xctr_out1 38 xctr_out2 39 vdd 40 vdd 41 vcxout 42 vss 43 vss2 44 ttn 45 test0 46 test1 47 vdd 48 vdd 49 clkmuxin 50 sd1_3 51 sd1_2 52 sd1_1 53 vss 54 sd1_0 55 sd0_3 56 sd0_2 57 sd0_1 58 vdd 59 sd0_0 60 startout 61 dvout_lp 62 dvout 63 muxout26 64 vss 65 muxout25 66 muxout24 67 muxout23 68 muxout22 69 vdd 70 muxout21 71 muxout20 72 muxout19 73 muxout18 74 vss 75 muxout17 76 muxout16 77 muxout15 78 muxout14 79 vdd 80 vdd 81 muxout13 82 muxout12 83 muxout11 84 muxout10 85 vss 86 muxout9 87 muxout8 88 muxout7 89 muxout6 90 vdd 91 muxout5 92 muxout4 93 muxout3 94 muxout2 95 muxout1 96 muxout0 97 vss 98 clk18 99 pllvdd 100 pllagnd 101 plllp2 102 pllvss 103 vss2 104 p_s 105 asn 106 csn 107 read 108 d_7 109 vdd 110 vdd 111 d_6 112 d_5 113 d_4 114 d_3 115 d_2 116 d_1 117 d_0 118 vss 119 vss2 120 vss 121 afcout 122 vdd 123 vss2 124 a_4 125 a_3 126 a2 127 a1 128 a0 129 digin_0 130 digin_1 131 vdd 132 digin_2 133 digin_3 134 digin_4 135 vss 136 vdd 137 digin_5 138 digin_6 139 tiddtn 140 vss2 141 digin_7 142 digin_8 143 digin_9 144 plltstclk 145 plltstsel 146 procq 147 vdd 148 vdd 149 agcout 150 vss 151 adcpd 152 adcgvss 153 adcvss 154 adcvrefp 155 adcvrefn 156 avin 157 ibias 158 adcvdd 159 adcgvdd 160 signal pin signal pin signal pin
pinouts 6-13 table 6.9 pin list by name signal pin a0 129 a1 128 a2 127 a3 126 a4 125 adcgvdd 160 adcgvss 153 adcpd 152 adcvdd 159 adcvrefn 156 adcvrefp 155 adcvss 154 afcout 122 agcout 150 asn 106 avin 157 clk18 99 clkmuxin 50 clkout54 34 csn 107 d0 118 d1 117 d2 116 d3 115 d4 114 d5 113 d6 112 d7 109 digin0 130 digin1 131 digin2 133 digin3 134 digin4 135 digin5 138 digin6 139 digin7 142 digin8 143 digin9 144 dtackn 35 dvout 63 dvout_lp 62 ibias 158 intn 36 muxin0 5 muxin1 6 muxin2 8 muxin3 9 muxin4 10 muxin5 11 muxin6 12 muxin7 14 muxin8 15 muxin9 16 muxin10 17 muxin11 18 muxin12 21 muxin13 22 muxin14 23 muxin15 24 muxin16 26 muxout0 97 muxout1 96 muxout2 95 muxout3 94 muxout4 93 muxout5 92 muxout6 90 muxout7 89 muxout8 88 muxout9 87 muxout10 85 muxout11 84 muxout12 83 muxout13 82 muxout14 79 muxout15 78 muxout16 77 muxout17 76 muxout18 74 muxout19 73 muxout20 72 muxout21 71 muxout22 69 muxout23 68 muxout24 67 muxout25 66 muxout26 64 pllagnd 101 plllp2 102 plltstclk 145 plltstsel 146 pllvdd 100 pllvss 103 procq 147 read 108 reset 20 p_s 105 sd0_0 60 sd0_1 58 sd0_2 57 sd0_3 56 sd1_2 52 sd1_0 55 sd1_1 53 sd1_3 51 startout 61 tck 28 tdi 30 tdo 33 test0 46 test1 47 tiddtn 140 tms 29 tresetn 27 ttn 45 vcxout 42 vdd 40 vdd 41 vdd 49 vdd 59 vdd 70 vdd 80 vdd 81 vdd 91 vdd 111 vdd 123 vdd 137 vdd 149 vdd 1 vdd 13 vdd 25 vdd 48 vdd 110 vdd 132 vdd 148 vss 32 vss 43 vss 54 vss 65 vss 75 vss 86 vss 98 vss 119 vss 121 vss 136 vss 151 vss2 7 vss2 19 vss2 31 vss2 44 vss2 104 vss2 120 vss2 124 vss2 141 xctr_in0 2 xctr_in1 3 xctr_in2 4 xctr_out0 37 xctr_out1 38 xctr_out2 39 signal pin signal pin signal pin
6-14 speci?cations 6.4.2 pin layout figure 6.4 illustrates the L64780 package pin layout. figure 6.4 package pin layout vdd xctr_in_1 xctr_in_2 muxin_0 muxin_1 vss2 muxin_2 muxin_3 muxin_4 muxin_5 muxin_6 xctr_in_0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 L64780 (pqfpt 160 package, top view) (body size 28 x 28 x 3.4 mm) (tip to tip dimension: 31.2 mm) (external lead pitch: 0.65 mm) vdd muxin_7 muxin_9 muxin_8 muxin_10 muxin_11 vdd vcxout vss vss2 ttn test0 test1 vdd vdd clkmuxin sd1_3 vdd muxout_13 muxout_12 muxout_11 muxout_10 vss muxout_9 muxout_8 muxout_7 muxout_6 muxout_2 muxout_4 muxout_3 muxout_1 muxout_0 vss pllvdd pllagnd d_6 d_5 d_4 d_3 d_2 d_1 d_0 vss2 vss afcout vss a_4 a_3 a_2 a_1 a_0 digin_0 digin_1 vdd vss2 vdd digin_2 digin_3 agcout vdd tiddtn digin_6 reset vss2 muxin_12 muxin_13 muxin_14 muxin_15 vdd muxin_16 tresetn tck tms tdi vss2 vss tdo clkout54 dtackn intn xctr_out_0 xctr_out_1 xctr_out_2 vdd sd1_2 sd1_1 vss sd1_0 sd0_3 sd0_2 sd0_1 vdd sd0_0 startout dvout_lp dvout muxout_26 vss muxout_25 muxout_24 muxout_23 muxout_22 vdd muxout_21 muxout_20 muxout_19 muxout_18 vss muxout_17 muxout_16 muxout_15 muxout_14 vdd muxout_5 vdd clk18 vdd vdd d_7 read csn asn p_s vss2 pllvss plllp2 digin_5 vdd vss digin_4 vdd procq plltstsel plltstclk digin_9 digin_8 digin_7 vss2 avin adcvrefn adcvrefp adcvss adcgvss adcpd vss adcgvdd adcvdd ibias ( package code: um55)
mechanical drawing 6-15 6.5 mechanical drawing figure 6.5 shows the mechanical drawing for the L64780 160-pin pqfp. figure 6.5 160 pqfp mechanical drawing: top and side views impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code um55.
6-16 speci?cations figure 6.6 160 pqfp mechanical drawing: detail impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code um55.
a-1 appendix a programming the L64780 using the serial bus interface this appendix discusses how to program the L64780 internal registers and data tables using the serial bus protocol. this appendix is intended primarily for system programmers who are developing software drivers using the serial bus. it consists of the following sections: section a.1, serial bus protocol overview, page a-2 section a.2, programming the slave address using the serial bus, page a-3
a-2 programming the L64780 using the serial bus interface a.1 serial bus protocol overview the multimaster serial bus interface has two one-bit lines: a0 (serial clock), and d0 (serial data). these are connected to the bus (see figure a.1 ). external pullup resistors hold the bus at a logic 1 when it is not in operation. see the serial bus protocol documentation for a detailed explanation and electrical characteristics. d[7:1] are used to set the serial bus slave address. when using the serial bus, d[7:1] must be hardwired to set the appropriate device slave address. select the serial bus mode on the L64780 by asserting p_s. features of the serial bus protocol include: two one-bit lines: a0 and d0. d0: serial data. a0: serial clock (maximum frequency = 400 khz). a0 and d0 have external pull-up resistors (the bus is normally high). the master always generates the clock, a0, and cycle start/stop conditions. figure a.1 provides an overview illustration of the serial bus. figure a.1 serial bus overview d0 a0 serial bus compliant device 5.0v 5.0v serial bus compliant device
programming the slave address using the serial bus a-3 a.2 programming the slave address using the serial bus a general call (master issues a start condition followed by eight zeroes) is used to address every device on the serial bus. any device that requires information to be supplied through this general call must acknowledge the cycle. figure a.2 general call address a.2.1 write cycle using the serial bus the following steps describe a write cycle using the serial bus. 1. the cycle is started by the master issuing a start condition. 2. the 7-bit slave address is transmitted. 3. the r/w bit is reset to 0 and transmitted, indicating a write cycle. 4. the addressed slave acknowledges the reception of the slave address by driving sda low in the ack cycle. 5. the master sends the 8-bit address. 6. the addressed slave acknowledges the reception of the address by driving sda low in the ack cycle. 7. the master sends the 8-bit data. 8. the addressed slave acknowledges the reception of the data by driving sda low in the ack cycle. 9. the master terminates the cycle by issuing a stop condition. 0000 00 00 x a xxxx x ax0 s general call addr. s: start condition a: acknowledge cycle x: dont care
a-4 programming the L64780 using the serial bus interface a.2.2 read cycle using the serial bus 1. the cycle is started with the start condition. 2. the 7-bit slave address is transmitted. 3. the r/w bit is reset to 0 and transmitted, indicating a write cycle. 4. the addressed slave acknowledges the reception of the slave address by driving sda low in the ack cycle. 5. the master sends the 8-bit address. 6. the addressed slave acknowledges the reception of the address by driving sda low in the ack cycle. 7. the master issues another start condition. 8. the 7-bit slave address is transmitted. 9. the r/w bit is set to 1 bit and transmitted, indicating a read cycle. 10. the addressed slave acknowledges the reception of the slave address by driving sda low in the ack cycle. 11. the slave starts transmitting the data. 12. the master must acknowledge receipt of the data by driving sda low during the ack cycle. 13. the master terminates the cycle by issuing a stop condition.
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u.s. distributors by state a. e. avnet electronics http://www.hh.avnet.com b. m. bell microproducts, inc. (for habs) http://www.bellmicro.com i. e. insight electronics http://www.insight-electron- ics.com w. e. wyle electronics http://www.wyle.com alabama daphne i. e. tel: 334.626.6190 huntsville a. e. tel: 256.837.8700 i. e. tel: 256.830.1222 w. e. tel: 800.964.9953 alaska a. e. tel: 800.332.8638 arkansas w. e. tel: 972.235.9953 arizona phoenix a. e. tel: 480.736.7000 b. m. tel: 602.267.9551 w. e. tel: 800.528.4040 tempe i. e. tel: 480.829.1800 tucson a. e. tel: 520.742.0515 california agoura hills b. m. tel: 818.865.0266 irvine a. e. tel: 949.789.4100 b. m. tel: 949.470.2900 i. e. tel: 949.727.3291 w. e. tel: 800.626.9953 los angeles a. e. tel: 818.594.0404 w. e. tel: 800.288.9953 sacramento a. e. tel: 916.632.4500 w. e. tel: 800.627.9953 san diego a. e. tel: 858.385.7500 b. m. tel: 858.597.3010 i. e. tel: 800.677.6011 w. e. tel: 800.829.9953 san jose a. e. tel: 408.435.3500 b. m. tel: 408.436.0881 i. e. tel: 408.952.7000 santa clara w. e. tel: 800.866.9953 woodland hills a. e. tel: 818.594.0404 westlake village i. e. tel: 818.707.2101 colorado denver a. e. tel: 303.790.1662 b. m. tel: 303.846.3065 w. e. tel: 800.933.9953 englewood i. e. tel: 303.649.1800 connecticut cheshire a. e. tel: 203.271.5700 i. e. tel: 203.272.5843 wallingford w. e. tel: 800.605.9953 delaware north/south a. e. tel: 800.526.4812 tel: 800.638.5988 b. m. tel: 302.328.8968 w. e. tel: 856.439.9110 florida altamonte springs b. m. tel: 407.682.1199 i. e. tel: 407.834.6310 boca raton i. e. tel: 561.997.2540 clearwater i. e. tel: 727.524.8850 fort lauderdale a. e. tel: 954.484.5482 w. e. tel: 800.568.9953 miami b. m. tel: 305.477.6406 orlando a. e. tel: 407.657.3300 w. e. tel: 407.740.7450 tampa w. e. tel: 800.395.9953 st. petersburg a. e. tel: 727.507.5000 georgia atlanta a. e. tel: 770.623.4400 b. m. tel: 770.980.4922 w. e. tel: 800.876.9953 duluth i. e. tel: 678.584.0812 hawaii a. e. tel: 800.851.2282 idaho a. e. tel: 801.365.3800 w. e. tel: 801.974.9953 illinois north/south a. e. tel: 847.797.7300 tel: 314.291.5350 chicago b. m. tel: 847.413.8530 w. e. tel: 800.853.9953 schaumburg i. e. tel: 847.885.9700 indiana fort wayne i. e. tel: 219.436.4250 w. e. tel: 888.358.9953 indianapolis a. e. tel: 317.575.3500 iowa w. e. tel: 612.853.2280 cedar rapids a. e. tel: 319.393.0033 kansas w. e. tel: 303.457.9953 kansas city a. e. tel: 913.663.7900 lenexa i. e. tel: 913.492.0408 kentucky w. e. tel: 937.436.9953 central/northern/ western a. e. tel: 800.984.9503 tel: 800.767.0329 tel: 800.829.0146 louisiana w. e. tel: 713.854.9953 north/south a. e. tel: 800.231.0253 tel: 800.231.5575 maine a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 maryland baltimore a. e. tel: 410.720.3400 w. e. tel: 800.863.9953 columbia b. m. tel: 800.673.7461 i. e. tel: 410.381.3131 massachusetts boston a. e. tel: 978.532.9808 w. e. tel: 800.444.9953 burlingtonr i. e. tel: 781.270.9400 marlborough b. m. tel: 508.480.9099 woburn b. m. tel: 781.933.9010 michigan brighton i. e. tel: 810.229.7710 detroit a. e. tel: 734.416.5800 w. e. tel: 888.318.9953 minnesota champlin b. m. tel: 800.557.2566 eden prairie b. m. tel: 800.255.1469 minneapolis a. e. tel: 612.346.3000 w. e. tel: 800.860.9953 st. louis park i. e. tel: 612.525.9999 mississippi a. e. tel: 800.633.2918 w. e. tel: 256.830.1119 missouri w. e. tel: 630.620.0969 st. louis a. e. tel: 314.291.5350 i. e. tel: 314.872.2182 montana a. e. tel: 800.526.1741 w. e. tel: 801.974.9953 nebraska a. e. tel: 800.332.4375 w. e. tel: 303.457.9953 nevada las vegas a. e. tel: 800.528.8471 w. e. tel: 702.765.7117 new hampshire a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 new jersey north/south a. e. tel: 201.515.1641 tel: 609.222.6400 mt. laurel i. e. tel: 609.222.9566 pine brook w. e. tel: 800.862.9953 parsippany i. e. tel: 973.299.4425 wayne w. e. tel: 973.237.9010 new mexico w. e. tel: 480.804.7000 albuquerque a. e. tel: 505.293.5119
u.s. distributors by state (continued) new york hauppauge i. e. tel: 516.761.0960 long island a. e. tel: 516.434.7400 w. e. tel: 800.861.9953 rochester a. e. tel: 716.475.9130 i. e. tel: 716.242.7790 w. e. tel: 800.319.9953 smithtown b. m. tel: 800.543.2008 syracuse a. e. tel: 315.449.4927 north carolina raleigh a. e. tel: 919.859.9159 i. e. tel: 919.873.9922 w. e. tel: 800.560.9953 north dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 ohio cleveland a. e. tel: 216.498.1100 w. e. tel: 800.763.9953 dayton a. e. tel: 614.888.3313 i. e. tel: 937.253.7501 w. e. tel: 800.575.9953 strongsville b. m. tel: 440.238.0404 valley view i. e. tel: 216.520.4333 oklahoma w. e. tel: 972.235.9953 tulsa a. e. tel: 918.459.6000 i. e. tel: 918.665.4664 oregon beavertonr b. m. tel: 503.524.0787 i. e. tel: 503.644.3300 portland a. e. tel: 503.526.6200 w. e. tel: 800.879.9953 pennsylvania mercer i. e. tel: 412.662.2707 pittsburgh a. e. tel: 412.281.4150 w. e. tel: 440.248.9996 philadelphia a. e. tel: 800.526.4812 b. m. tel: 215.741.4080 w. e. tel: 800.871.9953 rhode island a. e. 800.272.9255 w. e. tel: 781.271.9953 south carolina a. e. tel: 919.872.0712 w. e. tel: 919.469.1502 south dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 tennessee w. e. tel: 256.830.1119 east/west a. e. tel: 800.241.8182 tel: 800.633.2918 texas austin a. e. tel: 512.219.3700 b. m. tel: 512.258.0725 i. e. tel: 512.719.3090 w. e. tel: 800.365.9953 dallas a. e. tel: 214.553.4300 b. m. tel: 972.783.4191 w. e. tel: 800.955.9953 el paso a. e. tel: 800.526.9238 houston a. e. tel: 713.781.6100 b. m. tel: 713.917.0663 w. e. tel: 800.888.9953 richardson i. e. tel: 972.783.0800 rio grande valley a. e. tel: 210.412.2047 stafford i. e. tel: 281.277.8200 utah centerville b. m. tel: 801.295.3900 murray i. e. tel: 801.288.9001 salt lake city a. e. tel: 801.365.3800 w. e. tel: 800.477.9953 vermont a. e. tel: 800.272.9255 w. e. tel: 716.334.5970 virginia a. e. tel: 800.638.5988 w. e. tel: 301.604.8488 washington kirkland i. e. tel: 425.820.8100 seattle a. e. tel: 425.882.7000 w. e. tel: 800.248.9953 west virginia a. e. tel: 800.638.5988 wisconsin milwaukee a. e. tel: 414.513.1500 w. e. tel: 800.867.9953 wauwatosa i. e. tel: 414.258.5338 wyoming a. e. tel: 800.332.9326 w. e. tel: 801.974.9953
sales of?ces and design resource centers lsi logic corporation corporate headquarters tel: 408.433.8000 fax: 408.433.8989 north america california costa mesa - mint technology tel: 949.752.6468 fax: 949.752.6868 irvine tel: 949.809.4600 fax: 949.809.4444 pleasanton design center tel: 925.730.8800 fax: 925.730.8700 san diego tel: 858.467.6981 fax: 858.496.0548 silicon valley tel: 408.433.8000 fax: 408.954.3353 wireless design center tel: 858.350.5560 fax: 858.350.0171 colorado boulder tel: 303.447.3800 fax: 303.541.0641 colorado springs tel: 719.533.7000 fax: 719.533.7020 fort collins tel: 970.223.5100 fax: 970.206.5549 florida boca raton tel: 561.989.3236 fax: 561.989.3237 georgia alpharetta tel: 770.753.6146 fax: 770.753.6147 illinois oakbrook terrace tel: 630.954.2234 fax: 630.954.2235 kentucky bowling green tel: 270.793.0010 fax: 270.793.0040 maryland bethesda tel: 301.897.5800 fax: 301.897.8389 massachusetts waltham tel: 781.890.0180 fax: 781.890.6158 burlington - mint technology tel: 781.685.3800 fax: 781.685.3801 minnesota minneapolis tel: 612.921.8300 fax: 612.921.8399 new jersey red bank tel: 732.933.2656 fax: 732.933.2643 cherry hill - mint technology tel: 609.489.5530 fax: 609.489.5531 new york fairport tel: 716.218.0020 fax: 716.218.9010 north carolina raleigh tel: 919.785.4520 fax: 919.783.8909 oregon beaverton tel: 503.645.0589 fax: 503.645.6612 texas austin tel: 512.388.7294 fax: 512.388.4171 plano tel: 972.244.5000 fax: 972.244.5001 houston tel: 281.379.7800 fax: 281.379.7818 canada ontario ottawa tel: 613.592.1263 fax: 613.592.3253 international france paris lsi logic s.a. immeuble europa tel: 33.1.34.63.13.13 fax: 33.1.34.63.13.19 germany munich lsi logic gmbh tel: 49.89.4.58.33.0 fax: 49.89.4.58.33.108 stuttgart tel: 49.711.13.96.90 fax: 49.711.86.61.428 italy milano lsi logic s.p.a. tel: 39.039.687371 fax: 39.039.6057867 japan tokyo lsi logic k.k. tel: 81.3.5463.7821 fax: 81.3.5463.7820 osaka tel: 81.6.947.5281 fax: 81.6.947.5287 korea seoul lsi logic corporation of korea ltd tel: 82.2.528.3400 fax: 82.2.528.2250 the netherlands eindhoven lsi logic europe ltd tel: 31.40.265.3580 fax: 31.40.296.2109 singapore singapore lsi logic pte ltd tel: 65.334.9061 fax: 65.334.4749 tel: 65.835.5040 fax: 65.732.5047 sweden stockholm lsi logic ab tel: 46.8.444.15.00 fax: 46.8.750.66.47 taiwan taipei lsi logic asia, inc. taiwan branch tel: 886.2.2718.7828 fax: 886.2.2718.8869 united kingdom bracknell lsi logic europe ltd tel: 44.1344.426544 fax: 44.1344.481039 sales of?ces with design resource centers
international distributors australia new south wales reptechnic pty ltd tel: 612.9953.9844 fax: 612.9953.9683 belgium acal nv/sa tel: 32.2.7205983 fax: 32.2.7251014 china beijing lsi logic international services inc. tel: 86.10.6804.2534 fax: 86.10.6804.2521 france rungis cedex azzurri technology france tel: 33.1.41806310 fax: 33.1.41730340 germany haar ebv elektronik tel: 49.89.4600980 fax: 49.89.46009840 munich avnet emg gmbh tel: 49.89.45110102 fax: 49.89.42.27.75 wuennenberg-haaren peacock ag tel: 49.2957.79.1692 fax: 49.2957.79.9341 hong kong hong kong avt industrial ltd tel: 852.2428.0008 fax: 852.2401.2105 eastele tel: 852.2798.8860 fax: 852.2305.0640 india bangalore spike technologies india private ltd tel: 91.80.664.5530 fax: 91.80.664.9748 israel tel aviv eastronics ltd tel: 972.3.6458777 fax: 972.3.6458666 japan tokyo global electronics corporation tel: 81.3.3260.1411 fax: 81.3.3260.7100 technical center tel: 81.471.43.8200 yokohama-city macnica corporation tel: 81.45.939.6140 fax: 81.45.939.6141 the netherlands eindhoven acal nederland b.v. tel: 31.40.2.502602 fax: 31.40.2.510255 switzerland brugg lsi logic sulzer ag tel: 41.32.3743232 fax: 41.32.3743233 taiwan taipei avnet-mercuries corporation, ltd tel: 886.2.2516.7303 fax: 886.2.2505.7391 lumax international corporation, ltd tel: 886.2.2788.3656 fax: 886.2.2788.3568 prospect technology corporation, ltd tel: 886.2.2721.9533 fax: 886.2.2773.3756 serial semiconductor corporation, ltd tel: 886.2.2579.5858 fax: 886.2.2570.3123 united kingdom maidenhead azzurri technology ltd tel: 44.1628.826826 fax: 44.1628.829730 swindon ebv elektronik tel: 44.1793.849933 fax: 44.1793.859555 sales of?ces with design resource centers

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